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부품번호 AD9287 기능
기능 Serial LVDS 1.8 V ADC
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AD9287 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
4 ADCs integrated into 1 package
133 mW ADC power per channel at 100 MSPS
SNR = 49 dB (to Nyquist)
ENOB = 7.85 bits
SFDR = 65 dBc (to Nyquist)
Excellent linearity
DNL = ±0.2 LSB (typical)
INL = ±0.2 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
295 MHz full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9287 is a quad, 8-bit, 100 MSPS analog-to-digital con-
verter (ADC) with an on-chip sample-and-hold circuit designed
for low cost, low power, small size, and ease of use. The product
operates at a conversion rate of up to 100 MSPS and is optimized
for outstanding dynamic performance and low power in
applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Quad, 8-Bit, 100 MSPS,
Serial LVDS 1.8 V ADC
AD9287
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD DRGND
VIN + A
VIN – A
VIN + B
VIN – B
VIN + C
VIN – C
VIN + D
VIN – D
VREF
SENSE
REFT
REFB
AD9287
T/H
T/H
T/H
T/H
PIPELINE
ADC
8
8
PIPELINE
ADC
PIPELINE
ADC
8
PIPELINE
ADC
8
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
REF
SELECT
+– 0.5V
SERIAL PORT
INTERFACE
DATA RATE
MULTIPLIER
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
FCO+
FCO–
DCO+
DCO–
RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK–
Figure 1.
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9287 is available in an RoHS compliant, 48-lead LFCSP. It
is specified over the industrial temperature range of −40°C to
+85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-
saving package.
2. Low power of 133 mW/channel at 100 MSPS.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 400 MHz and supports
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of flexible
features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9219 (10-bit),
AD9228 (12-bit), and AD9259 (14-bit).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9287 pdf, 반도체, 판매, 대치품
Data Sheet
REVISION HISTORY
1/15—Rev. E to Rev. F
Changes to Figure 2...........................................................................8
Changes to Figure 4...........................................................................9
12/11—Rev. D to Rev. E
Changes to Output Signals Section and Figure 60......................35
Change to Default Operation and Jumper Selection Settings
Section ..............................................................................................36
Changes to Figure 63 ......................................................................39
Added Endnote 2 in Ordering Guide ...........................................51
4/10—Rev. C to Rev. D
Changes to Table 16 ........................................................................33
Updated Outline Dimensions........................................................51
Changes to Ordering Guide...........................................................51
1/10—Rev. B to Rev. C
Updated Outline Dimensions........................................................51
Changes to Ordering Guide...........................................................52
7/07—Rev. A to Rev. B
Changes to Figure 2 and Figure 4....................................................7
Changes to Table 17 ........................................................................48
5/07—Rev. 0 to Rev. A
Changes to Logic Output (SDIO/ODM)........................................5
Change to Pipeline Latency .............................................................6
Added Endnote 2 to Table 4.............................................................6
Changes to Figure 2 to Figure 4.......................................................7
Changes to Figure 10 ......................................................................12
AD9287
Change to Figure 15 Caption.........................................................14
Changes to Figure 29 ......................................................................16
Changes to Figure 41 ......................................................................19
Changes to Clock Duty Cycle Considerations Section ..............20
Changes to Power Dissipation and Power-Down Mode Section ...21
Changes to Figure 50 to Figure 52 Captions ...............................23
Change to Table 8............................................................................23
Changes to Table 9 Endnote ..........................................................24
Changes to Digital Outputs and Timing Section........................25
Added Table 10 ................................................................................25
Changes to RBIAS Pin Section......................................................26
Deleted Figure 53 and Figure 54 ...................................................26
Changes to Figure 56 ......................................................................27
Changes to Hardware Interface Section.......................................28
Added Figure 57 ..............................................................................29
Changes to Table 15 ........................................................................29
Changes to Reading the Memory Map Table Section ................30
Changes to Output Signals Section...............................................34
Changes to Figure 60 ......................................................................34
Changes to Default Operation and
Jumper Selection Settings Section ................................................35
Changes to Alternative Analog Input Drive
Configuration Section ....................................................................36
Changes to Figure 63 ......................................................................38
Changes to Table 17 ........................................................................46
Changes to Ordering Guide...........................................................50
7/06—Revision 0: Initial Version
Rev. F | Page 3 of 51

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AD9287 전자부품, 판매, 대치품
AD9287
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D + x, D − x),
(Low Power, Reduced Signal Option)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temp
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Min
250
1.2
1.2
1.2
0
247
1.125
Typ Max Unit
CMOS/LVDS/LVPECL
1.2
20
1.5
mV p-p
V
kΩ
pF
3.6 V
0.3 V
30 kΩ
0.5 pF
3.6 V
0.3 V
70 kΩ
0.5 pF
DRVDD + 0.3 V
0.3 V
30 kΩ
2 pF
1.79 V
0.05 V
LVDS
Offset binary
454
1.375
mV
V
Full 150
Full 1.10
LVDS
Offset binary
250
1.30
mV
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
2 This is specified for LVDS and LVPECL only.
3 This is specified for 13 SDIO pins sharing the same connection.
Rev. F | Page 6 of 51

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