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PDF 56F802 Data sheet ( Hoja de datos )
| Número de pieza | 56F802 | |
| Descripción | 16-bit Digital Signal Controllers | |
| Fabricantes | Freescale Semiconductor | |
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56F802
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F802
Rev. 9
01/2007
freescale.com
1 page  
56F802 Description
• Computer-Operating Properly (COP) watchdog timer
• External interrupts via GPIO
• Trimmable on-chip relaxation oscillator
• External reset pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• Integrated power supervisor
1.2 56F802 Description
The 56F802 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and
compact program code, the 56F802 is well-suited for many applications. The 56F802 includes many
peripherals that are especially useful for applications such as motion control, home appliances, encoders,
tachometers, limit switches, power supply and control, engine management, and industrial control for
power, lighting, automation and HVAC.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F802 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F802 also provides and up to 4
General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F802 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.
A key application-specific feature of the 56F802 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs
to enhance motor control functionality. Complementary operation permits programmable dead-time
Freescale Semiconductor
56F802 Technical Data, Rev. 9
5
5 Page 
2.3 Interrupt and Program Control Signals
Interrupt and Program Control Signals
No. of
Pins
1
Signal
Name
RESET
Table 2-5 Program Control Signals
Signal
Type
Input
(Schmitt)
State During
Reset
Input
Signal Description
Reset—This input is a direct hardware reset on the processor. When
RESET is asserted low, the controller is initialized and placed in the
Reset state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the EXTBOOT pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
2.4 Pulse Width Modulator (PWM) Signals
Table 2-6 Pulse Width Modulator (PWMA) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6 PWMA0-5 Output
Tri-stated PWMA0-5— These are six PWMA output pins.
1 FAULTA0 Input
(Schmitt)
Input
FAULTA0 —This fault input is used for disabling selected PWMA
outputs in cases where fault conditions originate off-chip.
2.5 Serial Communications Interface (SCI) Signals
No. of
Pins
1
Table 2-7 Serial Communications Interface (SCI0) Signals
Signal
Name
TXD0
Signal
Type
Output
State During
Reset
Input
Signal Description
Transmit Data (TXD0)—SCI0 transmit data output
GPIOB0 Input/Ou
tput
Input
Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as an input or output pin.
After reset, the default state is SCI output.
Freescale Semiconductor
56F802 Technical Data, Rev. 9
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 56F802.PDF ] | |
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