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PDF HT49RU80 Data sheet ( Hoja de datos )
| Número de pieza | HT49RU80 | |
| Descripción | LCD Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
HT49RU80/HT49CU80
LCD Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0017E Controlling the Read/Write Function of the HT24 Series EEPROM Using the HT49 Series MCUs
- HA0024E Using the RTC in the HT49 MCU Series
- HA0025E Using the Time Base in the HT49 MCU Series
- HA0026E Using the I/O Ports on the HT49 MCU Series
- HA0027E Using the Timer/Event Counter in the HT49 MCU Series
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· 8 input lines and 7 output lines
· 16 bidirectional I/O lines
· Two external interrupt inputs
· One 8-bit and two 16-bit programmable timer/event
counters with PFD - programmable frequency divider
function
· LCD driver with 48´2, 48´3 or 47´4 segments
· 16K´16 program memory
· 576´8 data memory RAM
· Real Time Clock - RTC
· RTC 8-bit prescaler
· Watchdog Timer
· Buzzer output
· On-chip crystal, RC and 32768Hz crystal oscillator
· HALT function and wake-up feature reduce power
consumption
· 16-level subroutine nesting
· UART - Universal Asynchronous Receiver Transmit-
ter
· Bit manipulation instruction
· 16-bit table read instruction
· Up to 0.5ms instruction cycle with 8MHz system clock
· 63 powerful instructions
· All instructions executed within 1 or 2 machine cycles
· Low voltage reset/detector functions
· 100-pin QFP package
General Description
These devices are 8-bit, high performance, RISC archi-
tecture microcontrollers specifically designed for a wide
range of LCD applications. The mask version, the
HT49CU80, is fully pin and functionally compatible with
the OTP version HT49RU80 device.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, power-down and wake-up functions
and buzzer driver in addition to a flexible and
configurable LCD interface, enhance the versatility of
these devices to control a wide range of LCD-based ap-
plication possibilities such as measuring scales, elec-
tronic multimeters, gas meters, timers, calculators,
remote controllers and many other LCD-based indus-
trial and home appliance applications.
The HT49CU80 is under development and will be avail-
able soon.
Rev. 1.00
DataSheet4 U .com
1 June 1, 2006
1 page  
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HT49RU80/HT49CU80
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
VDD Operating Voltage
VLCD
IDD1
IDD2
IDD3
IDD4
IDD5
ISTB1
ISTB2
LCD Power Supply (Note *)
Operating Current
(Crystal OSC, RC OSC)
Operating Current
(Crystal OSC, RC OSC)
Operating Current
(Crystal OSC, RC OSC)
Operating Current
(Crystal OSC, RC OSC)
Operating Current
(fSYS=RTC OSC)
Standby Current
(*fS=fSYS/4)
Standby Current
(*fS=RTC OSC)
ISTB3
Standby Current
(*fS=WDT OSC)
ISTB4
Standby Current
(*fS=RTC OSC)
ISTB5
Standby Current
(*fS=RTC OSC)
ISTB6
Standby Current
(*fS=WDT OSC)
ISTB7
Standby Current
(*fS=WDT OSC)
Test Conditions
VDD Conditions
LVR disabled, fSYS=4MHz
¾
LVR disabled, fSYS=8MHz
Min.
2.2
3.3
¾ VA£5.5V
2.2
3V No load, fSYS=4MHz,
5V UART Off
¾
¾
3V No load, fSYS=4MHz,
5V UART On
¾
¾
5V
No load, fSYS=8MHz,
UART Off
¾
5V
No load, fSYS=8MHz,
UART On
¾
3V
No load, UART Off
5V
¾
¾
3V No load, system HALT,
5V LCD Off at HALT, UART Off
¾
¾
3V No load, system HALT,
LCD On at HALT, C type,
5V UART Off
¾
¾
3V No load, system HALT
LCD On at HALT, C type,
5V UART Off
¾
¾
3V No load, system HALT,
LCD On at HALT, R type,
5V 1/2 bias, UART Off
¾
¾
3V No load, system HALT,
LCD On at HALT, R type,
5V 1/3 bias, UART Off
¾
¾
3V No load, system HALT,
LCD On at HALT, R type,
5V 1/2 bias, UART Off
¾
¾
3V No load, system HALT,
LCD On at HALT, R type,
5V 1/3 bias, UART Off
¾
¾
Typ.
¾
¾
¾
1
3
2
5
4
6
0.3
0.6
¾
¾
2.5
10
2
6
17
34
13
26
14
28
10
20
Ta=25°C
Max. Unit
5.5 V
5.5 V
5.5 V
2 mA
5 mA
4 mA
10 mA
8 mA
12 mA
0.6 mA
1 mA
1 mA
2 mA
5 mA
20 mA
5 mA
10 mA
30 mA
60 mA
25 mA
50 mA
25 mA
50 mA
20 mA
40 mA
Rev. 1.00
5 June 1, 2006
DataSheet4 U .com
5 Page 
www.DataSheet4U.com
HT49RU80/HT49CU80
Bit No.
0
1
2
3
4
5
6, 7
Label
C
AC
Z
OV
PDF
TO
¾
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
set by executing the ²HALT² instruction.
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
Unused bit, read as ²0²
STATUS (0AH) Register
is important, and if the subroutine is likely to corrupt the
status register, precautions should be taken to save it
properly.
Interrupts
The device provides two external interrupts, three inter-
nal timer/event counters interrupts, an internal time
base interrupt, an internal real time clock interrupt, and
an UART TX/RX interrupt. The interrupt control register
0, INTC0, and interrupt control register 1, INTC1, both
contain the interrupt control bits that are used to set the
enable/disable status and to record the interrupt request
flags.
Once an interrupt subroutine is serviced, other inter-
rupts are all blocked, by clearing the EMI bit. This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit in the
INTC0 or of INTC1 register may be set in order to allow
interrupt nesting. Once the stack is full, the interrupt re-
quest will not be acknowledged, even if the related inter-
rupt is enabled, until the SP is decremented. If
immediate service is desired, the stack should be pre-
vented from becoming full.
All interrupts provide a wake-up function. As an interrupt
is serviced, a control transfer occurs by pushing the con-
tents of the program counter onto the stack followed by
a branch to a subroutine at a specified program memory
location. Only the contents of the program counter is
pushed onto the stack. If the contents of the register or
of the status register is altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion on the INT0 or INT1 pins, which will result in their
their related interrupt request flags, EIF0 and EEF1, be-
ing set. After the interrupt is enabled, the stack is not full,
and a high to low transition occurs on the external inter-
rupt pins, a subroutine call to location 04H or 08H oc-
curs. When the interrupt service routine is serviced, the
interrupt request flags, EIF0 and EIF1, and the global
enable bit, EMI, are all cleared to disable other inter-
rupts.
The internal Timer/Event Counter 0 interrupt is
initialised by setting the Timer/Event Counter 0 interrupt
request flag, T0F. This will occur when the timer over-
flows. After the interrupt is enabled, and the stack is not
full, and T0F bit is set, a subroutine call to location 0CH
occurs. The related interrupt request flag, T0F, is reset,
and the EMI bit is cleared to disable further interrupts.
The Timer/Event Counter 1 is operated in the same
manner but its related interrupt request flag is T1F, and
its subroutine call location is 10H.
The UART interrupt is initialised by setting the interrupt
request flag, URF, that is caused by a regular UART re-
ceive signal, caused by a UART transmit signal. After
the interrupt is enabled, the stack is not full, and the URF
bit is set, a subroutine call to location 14H occurs. The
related interrupt request flag, URF, is reset and the EMI
bit is cleared to disable further interrupts.
The multi function interrupt is initialised by setting the in-
terrupt request flag, MFF, that is caused by a regular
internal Timer/Event Counter 2 overflow, caused by a
time base signal or caused by a real time clock signal.
After the interrupt is enabled, the stack is not full, and
the MFF bit is set, a subroutine call to location 18H oc-
curs. The related interrupt request flag, MFF, is reset
and the EMI bit is cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are all held until a ²RETI² in-
struction is executed or the EMI bit and the related inter-
rupt control bit are both set to 1 (if the stack is not full). To
return from the interrupt subroutine a ²RET² or ²RETI²
Rev. 1.00
11 June 1, 2006
DataSheet4 U .com
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