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SC-604 데이터시트 PDF




Sensory에서 제조한 전자 부품 SC-604은 전자 산업 및 응용 분야에서
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부품번호 SC-604 기능
기능 Speech And Music Processor
제조업체 Sensory
로고 Sensory 로고


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SC-604 데이터시트, 핀배열, 회로
www.DataSheet4U.com
SC-604
Speech And Music Processor
Data sheet
Features
Advanced, Integrated Speech Synthesizer for
High-Quality Sound
Operates up to 12.32 MHz (Performs up to 12
MIPS)
Slave Mode Enables Hours of Speech Using an
External Processor and Memory
Master Mode Allows 6.8 Minutes of Speech
Onboard
Supports High-Quality Synthesis Algorithms
such as MX, CX, Simple CX, LX, ADPCM, and
Polyphonic Music
Simultaneous Speech Plus Music Capabilities
Very Low-Power Operation, Ideal for Hand-Held
Devices
Low-Voltage Operation, Sustainable by Three
(3) Batteries
Reduced Power Standby Modes, Less Than 10
µA in Deep-Sleep Mode
16 General-Purpose I/O Pins (in Master Mode)
or 4 General-Purpose I/O Pins (in Slave Mode)
Resistor-Trimmed Oscillator or 32.768-kHz
Crystal Reference Oscillator
Slave Interface Logic Contains 64K Bytes-
Words Onboard ROM (2K Words Reserved)
640-Word RAM
Direct Speaker Drive, 32 (PDM)
One-Bit Comparator With Edge Detection
Interrupt Service
Serial Scan Port for In-Circuit Emulation,
Monitor, and Test
Available in Die Form or 64-Pin LQFP Package
Description
The SC-604 is a low-cost, mixed-signal
processor that combines a speech synthesizer
with a dedicated slave interface logic, general-
purpose I/O, onboard ROM, and direct speaker-
drive in a single package. The computational
unit uses a powerful new DSP that gives the SC-
604 unprecedented speed and computational
flexibility compared with previous devices of its
type. The SC-604 supports a variety of speech
and audio coding algorithms, providing a range
of options with respect to speech duration and
sound quality.
16-Bit
Microprocessor
640-words
RAM
SLAVE LOGIC
64K-Bytes ROM
SC-691 Block Diagram
10-Bit
DAC
TIMER 1
TIMER 2
COMPARATOR
PLLM
The device consists of a micro-DSP core,
embedded program and data memory, and a self-contained clock generation system. General-purpose
periphery is comprised of 16 bits of partially configurable I/O.
The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block
includes a computational unit (CU), data address unit, program address unit, two timers, eight-level interrupt
processor, and several system and control registers. The core processor gives the SC-604break-point capability
in emulation.
The processor is a Harvard type for efficient DSP algorithm execution, separating program and data memory
blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is
configured in 32K 17-bit words.
The total ROM space is divided into two areas:
1) The lower 2K words are reserved by Sensory, Inc. for a built-in self-test
2) The upper 30K is for user program and data space.
© 2002 Sensory Inc.
P/N 80-0208-B
1




SC-604 pdf, 반도체, 판매, 대치품
SC-604
Data sheet
Configure port A (PA0–PA7), PORT D2, and port D3 as input ports (default at reset). Write 0x00 to port A
(0x04) and 0x03 to port D (0x1C) control registers.
After the slave completes its initialization, the slave needs to inform the host that it is ready to read or write
data.
Note: the default mode for the MSP50C604 is the slave mode. The MSP50C604 can be set to master mode by
writing a 1 to port G bit 0. This is an internal bit that is not available on the MSP50C604 external pins.
Note: the initialization sequence given previously is a specific requirement for setting up the MSP50C604 in
slave mode. For the basic initialization requirements of the device, please refer to the MSP50C614 user’s guide
(SPSU014).
Write To Slave In The Slave Mode
The slave indicates it is ready to receive data from the host by dropping INRDY low. This is done by writing
low-high-low to port D (0x18) bit 0 (PD0).
On the falling edge of the internal PD0 pulse, INRDY toggles low, notifying the host that the slave is ready to
receive data.
The host writes data to the slave by setting R/W low and then pulsing the STROBE high-low-high.
The slave latches the data on the rising edge of the STROBE pulse and sets INRDY high.
An INT3 interrupt is generated as INRDY goes high completing the write cycle.
The latched data is read by the slave through port A (0x00) data register.
Read From Slave In The Slave Mode
When the slave has data for the host, it places the data in port C (0x10).
The slave then indicates that the data is ready by dropping OUTRDY low. This is done by writing low-high-
low to port D (0x18) bit 1 (PD1).
On the falling edge of the internal PD1 pulse, OUTRDY toggles low notifying the host that the slave is ready
to send data.
The host responds by setting R/W high and then pulsing STROBE high-low-high.
The host should latch the data before raising STROBE high.
This informs the slave that the data has been written to the host. The OUTRDY is pulled high by the slave at
the rising edge of STROBE.
An INT4 interrupt is generated as OUTRDY goes high completing the read cycle.
4
P/N 80-0208-B
© 2002 Sensory Inc.

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SC-604 전자부품, 판매, 대치품
Data Sheet
SC-604
Absolute Maximum Ratings
Absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1)
Supply current, IDD (see Note 2)
Input voltage range, VI (see Note 1)
Output voltage range, VO (see Note 1)
Storage temperature range, TA
-0.3 to 7 V
35 mA
-0.3 to VDD + 0.3 V
-0.3 to VDD + 0.3 V
-30°C to 125°C
WARNING:
Stressing the SC-604 beyond the “Absolute
Maximum Ratings” may cause permanent
damage. These are stress ratings only.
Operation beyond the “Operating Conditions” is
not recommended and extended exposure
beyond the “Operating Conditions” may affect
device reliability.
NOTES: 1. Unless otherwise noted, all voltages are measured with respect to VSS.
2. The total supply current includes the current out of all the I/O pins as well as the operating current of the device.
Recommended Operating Conditions
Supply voltage (with respect to VSS), VDD
CPU clock rate (as programmed), f(CPU)
Load resistance between DACP and DACM, R(DAC)
Operating free-air temperature, TA
Timing Requirements
MIN MAX UNIT
3 5.2 V
64 12,320 kHz
32
Device functionality 0
70 °C
t(RESET)
t1(WIDTH)
t2(WIDTH)
Reset_ low pulse width, while VDD is within specified limits
Pulse width required prior to a negative transition at pin PD3, PD5, or PF0 PF7
Pulse width required prior to a positive transition at pin PD2 or PD4
MIN
100
2
2
MAX
UNIT
ns
1/FCPU
1/FCPU
‡ While these pins are being used as interrupt inputs.
t(RESET)
t(RESET)
Figure 1: Initialization Timing Diagram
t1(WIDTH (PD3, PD5, or F port))
t2(WIDTH (PD2, or PD4))
t1(WIDTH)
t2(WIDTH)
Figure 2: External Interrupt Pin Pulse Width Requirements t1WIDTH and t2WIDTH
© 2002 Sensory Inc.
P/N 80-0208-B
7

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