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AT91FR40162S 데이터시트 PDF




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AT91FR40162S 데이터시트, 핀배열, 회로
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Features
Incorporates the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
256K Bytes of On-chip SRAM
– 32-bit Data Bus, Single-clock Cycle Access
1024K Words 16-bit Flash Memory (2M bytes)
– Single Voltage Read/Write,
– Sector Erase Architecture
– Erase Suspend Capability
– Low-power Operation
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
– Reset Input for Device Initialization
– Sector Program Unlock Command
– 128-bit Protection Register
– Factory-programmed AT91 Flash Memory Uploader Software
Fully Programmable External Bus Interface (EBI)
– Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes
– Software Programmable 8/16-bit External Data Bus
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
32 Programmable I/O Lines
3-channel 16-bit Timer/Counter
– 3 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Programmable Watchdog Timer
Advanced Power-saving Features
– CPU and Peripherals Can be De-activated Individually
Fully Static Operation:
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85° C
2.7V to 3.6V I/O Operating Range, 1.65V to 1.95V Core Operating Range
-40° C to 85° C Temperature Range
Available in a 121-ball 10 x 10 x 1.2 mm BGA Package with 0.8 mm Ball Pitch
AT91 ARM®
Thumb®
Microcontrollers
AT91FR40162S
Summary
Preliminary
1. Description
The AT91FR40162S is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core. The processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption.
The AT91FR40162S ARM microcontroller features 2 Mbits of on-chip SRAM and 2
Mbytes of Flash memory in a single compact 121-ball BGA package. Its high level of
integration and very small footprint make the device ideal for space-constrained appli-
cations. The high-speed on-chip SRAM enables a performance of up to 74 MIPs in
typical conditions with significant power reduction and EMC improvement over an
external SRAM implementation.
The Flash memory may be programmed via the JTAG/ICE interface or the factory-
programmed Flash Memory Uploader (FMU) using a single device supply, making the
AT91FR40162S suitable for in-system programmable applications.
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Table 3-1. AT91FR40162S Pin Description (Continued)
Module
Flash
Memory
Power
Name
NCSF
NBUSY
NRSTF
VDDIO
VDDCORE
GND
VPP
Function
Flash Memory Select
Flash Memory Busy Output
Flash Memory Reset Input
Power
Power
Ground
Write Protection
Type
Input
Output
Input
Power
Power
Ground
Input
Active
Level
Low
Low
Low
Low
Comments
Enables Flash Memory when pulled low
Flash RDY/BUSY signal; open-drain
Resets Flash to standard operating mode
All VDDIO, VDDCORE and all GND pins
MUST be connected to their respective
supplies by the shortest route
Provides data protection (Program/Erase)
when VPP input is below 0.4V
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AT91FR40162S
5.2.1
5.2.2
System Peripherals
The External Bus Interface (EBI) controls the external memory or peripheral devices via an 8-
or 16-bit databus and is programmed through the APB. Each chip select line has its own pro-
gramming register.
The Power-saving (PS) module implements the Idle Mode (ARM7TDMI core clock stopped
until the next interrupt) and enables the user to adapt the power consumption of the microcon-
troller to application requirements (independent peripheral clock control).
The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the inter-
nal peripherals and the four external interrupt lines (including the FIQ) to provide an interrupt
and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller, and,
using the Auto-vectoring feature, reduces the interrupt latency time.
The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user to
select specific pins for on-chip peripheral input/output functions, and general-purpose
input/output signal pins. The PIO controller can be programmed to detect an interrupt on a sig-
nal change from each line.
The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped
in a deadlock.
The Special Function (SF) module integrates the Chip ID, the Reset Status and the Protect
registers.
User Peripherals
Two USARTs, independently configurable, enable communication at a high baud rate in syn-
chronous or asynchronous mode. The format includes start, stop and parity bits and up to 8
data bits. Each USART also features a Timeout and a Time Guard register, facilitating the use
of the two dedicated Peripheral Data Controller (PDC) channels.
The 3-channel, 16-bit Timer Counter (TC) is highly programmable and supports capture or
waveform modes. Each TC channel can be programmed to measure or generate different
kinds of waves, and can detect and control two input/output signals. The TC has also 3 exter-
nal clock signals.
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