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기능 Integrated High Performance Dual UARTs
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OX16PCI952 데이터시트, 핀배열, 회로
www.DataSheet4U.com
FEATURES
OX16PCI952 DATA SHEET
Integrated High Performance Dual UARTs,
Parallel Port and 5.0v PCI interface
DS_B008A_00
Two 16C950 High performance UART channels
IEEE1284 Compliant SPP/EPP/ECP parallel port
Multi- function target PCI controller. Fully compliant to
PCI bus specification 2.2 and PCI Power Management
1.0.
Function access to pre-configure each UART and the
parallel port, prior to handover to generic device
drivers.
UARTs fully software compatible with 16C550- type
devices.
Baud rates up to 15Mbps in asynchronous mode and
60Mbps in external 1x clock mode
128-byte deep FIFO per transmitter and receiver
Flexible clock prescaler from 1 to 31.875
Automated in-band flow control using programmable
Xon/Xoff in both directions
DESCRIPTION
Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
Arbitrary trigger levels for receiver and transmitter
FIFO interrupts and automatic in-band and out-of-
band flow control
Infra-red (IrDA) receiver and transmitter operation
5, 6, 7, 8 and 9-bits data framing
Global Interrupt Status and readable FIFO levels to
facilitate implementation of efficient device drivers
Detection of bad data in the receiver FIFO
2 multi-purpose IO pins which can be configured as
interrupt inputs or ‘wake-up’ pins (via local registers).
Auto-detection of a range of optional MicrowireTM
compatible EEPROMs, to reconfigure device.
Operation via IO or memory mapping.
5.0V operation
128 pin TQFP package
The OX16PCI952 is a single chip solution for PCI-based
serial and parallel expansion add-in cards. It is a dual
function device, offering IO or memory mapped access to
the two ultra-high performance OX16C950 UARTs and the
bi-directional parallel port. These functions are defined by
Function 0 and Function 1, respectively. Serial port cards
with 2 serial ports and a parallel port can be designed
without redefining any device parameters.
Each UART channel in the OX16PCI952, is the fastest
available PC-compatible UART, offering data rates up to
15Mbps and 128-byte deep transmitter and receiver FIFOs.
The deep FIFOs reduce CPU overhead and allow
utilisation of higher data rates. Each UART channel is
software compatible with the widely used industry-standard
16C550 devices and compatibles, as well as the
OX16C95x family of high performance UARTs. In addition
to increased performance and FIFO size, the UARTs also
provide the full set of OX16C95x enhanced features
including automated in-band flow control, readable FIFO
levels, etc.
The parallel port is an IEEE 1284 compliant SPP, EPP and
ECP parallel port that fully supports the existing Centronics
interface. For legacy applications, the PCI resources have
been arranged so that the parallel port can be located at
standard I/O addresses
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
A set of local registers is available to enhance device driver
efficiency and reduce interrupt latency. Each internal UART
has features such as shadowed FIFO fill levels, an interrupt
source register and Good-Data Status, readable in
consecutive DWORD registers and is visible to logical
function0 in both IO space and memory space. The local
registers also provide additional controls for each UART
and the parallel port, to customise the device for the end-
users application.
The efficient 32-bit, 33MHz target-only interface is
compliant with the PCI bus specification version 2.2 and
version 1.0 of PCI Power Management Specification.
For full flexibility, all the default configuration register
values can be overwritten using an optional MicrowireTM
compatible serial EEPROM.
This EEPROM can also be used to provide function access
to pre-configure each UART into enhanced modes or pre-
configure the parallel port, prior to any PCI configuration
accesses and before control is handed to generic device
drivers.
MicrowireTM is a trade mark of National Semiconductor.
© Oxford Semiconductor 2001
OX16PCI952 Datasheet rev 1.1 – June 2001
Part No. OX16PCI952-TQFP- A




OX16PCI952 pdf, 반도체, 판매, 대치품
OXFORD SEMICONDUCTOR LTD.
OX16PCI952
1 PERFORMANCE COMPARISON
Feature
Internal serial channels
Integral 1284 Compliant parallel port
Multi- function PCI device
Support for PCI Power Management
Zero wait-state read/write operation
No. of available external interrupt pins
DWORD access to UART Interrupt Source
Registers & FIFO Levels
Good-Data status
Full Plug and Play with external EEPROM
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Sleep mode
Auto Xon/Xoff flow
Auto CTS#/RTS# flow
Auto DSR#/DTR# flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmitter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Software reset
Device ID
9-bit data frames
RS485 buffer enable
Infra-red (IrDA)
OX16PCI952
2
yes
yes
yes
yes
2
yes
yes
yes
yes
15 Mbps
60 Mbps
128
yes
yes
yes
yes
128
128
128
yes
yes
yes
248
yes
yes
yes
yes
yes
yes
16C552 + PCI
Bridge
0
no
no
no
no
2
no
no
yes
no
115 Kbps
n/a
16
no
no
no
no
4
1
n/a
no
no
no
n/a
no
no
no
no
no
no
16C652 + PCI
Bridge
0
no
no
no
no
2
no
no
yes
no
1.5 Mbps
n/a
64
yes
yes
yes
no
4
4
4
no
no
no
2
no
no
no
no
no
yes
Table 1: OX16PCI952 performance compared with PCI Bridge + generic UART/Parallel Port Combinations.
1.1 Improvements of the OX16PCI952 over discrete solutions:
Higher degree of integration:
The OX16PCI952 offers two internal ultra-high
performance 16C950 UARTs and one IEEE1284 compliant
bi-directional parallel port.
UART device driver efficiency is increased by using each
channel’s features such as the 128-byte deep transmitter &
receiver FIFOs, flexible clock options, automatic flow
control, programmable interrupt and flow control trigger
levels and readable FIFO levels. Data rates of each UART
is up to 60Mbps.
DataSheet Revision 1.1
Improved access timing:
Access to the internal UARTs require zero or one PCI wait
states. A PCI read transaction from an internal UART can
complete within five PCI clock cycles and a write
transaction to an internal UART can complete within four
PCI clock cycles.
Reduces interrupt latency:
The OX16PCI952 offers shadowed FIFO levels and
Interrupt status registers of the internal UARTs, as well as
general device interrupt status, to reduce the device driver
interrupt latency.
Page 4

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OX16PCI952 전자부품, 판매, 대치품
OXFORD SEMICONDUCTOR LTD.
3 PIN INFORMATION
Package : 128 TQFP. (14mm x 14mm)
OX16PCI952
96
Z_DSR[1] 97
Z_CTS[1]
Z_DTR[1]
Z_RTS[1] 100
EXT_DATA_OUT[1]
GND
VDD
EXT_DATA_IN[0]
Z_RI[0]
Z_DCD[0]
Z_DSR[0]
Z_CTS[0]
Z_DTR[0]
Z_RTS[0]
EXT_DATA_OUT[0]
110
GND
Z_INTA
Z_INTB
Z_RESET
GND
PCI_CLK
VDD
GND
Z_PME 120
AD31
AD30
AD29
AD28
AD27
AD26
AD25
GND 128
1
90 80
OX16PCI952
10 20
70 65
64 SEEPROM_CS
SEEPROM_DO
SEEPROM_DI
GND
60 MULTI IO 1
MULTI IO 0
VDD
GND
MODE0
TEST
GND
GND
AD0
AD1
50 AD2
AD3
AD4
AD5
VDD
GND
AD6
AD7
Z_CBE0
AD8
40 AD9
AD10
VDD
GND
AD11
AD12
AD13
33 A D 1 4
30 32
DataSheet Revision 1.1
Page 7

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