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PDF OX16PCI954 Data sheet ( Hoja de datos )

Número de pieza OX16PCI954
Descripción Integrated Quad UART and PCI interface
Fabricantes Oxford Semiconductor 
Logotipo Oxford Semiconductor Logotipo



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FEATURES
Four 16C950 High performance UART channels
8/32-bit Pass-through Local Bus
IEEE1284 EPP parallel port
Multi-function target PCI controller, fully PCI 2.2 and
PCI Power Management 1.0 compliant
UARTs fully software compatible with 16C550-type
devices.
Baud rates up to 15Mbps in asynchronous mode and
60Mbps in external 1x clock mode
128-byte deep FIFO per transmitter and receiver
Flexible clock prescaler from 1 to 31.875
Automated in-band flow control using programmable
Xon/Xoff in both directions
Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
DESCRIPTION
The OX16PCI954 is a single chip solution for PCI-based
serial and parallel expansion add-in cards. It is a dual
function PCI device, where function 0 offers four ultra-high
performance OX16C950 UARTs, and function 1 is
configurable to offer either an 8 bit Local Bus or a bi-
directional parallel port. Serial port cards with up to 8 ports
(or with 4 serial ports and a parallel port) can be designed
without redefining any device or timing parameters.
Each channel in the OX16PCI954, the fastest available
PC-compatible UART, offers data rates up to 15Mbps and
128-deep transmitter and receiver FIFOs. Deep FIFOs
reduce CPU overhead and allow utilisation of higher data
rates. Each channel is software compatible with the widely
used industry-standard 16C550 devices and compatibles
as well as the OX16C95x family of high performance
UARTs. In addition to increased performance and FIFO
size, the UARTs also provide the full set of OX16C95x
enhanced features including automated in-band flow
control, readable FIFO levels etc.
The efficient 32-bit, 33MHz target-only PCI interface is
compliant with version 2.2 of the PCI Bus Specification and
version 1.0 of PCI Power Management Specification. For
applications that do not require the internal parallel port or
the local Bus, card designers can assign a Subsystem
Vendor ID and a Subsystem ID using 32 input pins. If the
UARTs are not required, the Local Bus can be extended
from 8-bit operation to a full 32-bit pass-through interface.
OX16PCI954
Integrated Quad UART
and PCI interface
Arbitrary trigger levels for receiver and transmitter
FIFO interrupts and automatic in-band and out-of-
band flow control
Infra-red (IrDA) receiver and transmitter operation
9-bit data framing as well as 5,6,7 and 8
12 multi-purpose IO pins which can be configured as
interrupt input pins
Can be reconfigured using optional non-volatile
configuration memory (EEPROM)
Global Interrupt Status and readable FIFO levels to
facilitate implementation of efficient device drivers
Operation via IO or memory mapping.
Detection of bad data in the receiver FIFO
5.0V operation
160 TQFP package
For full flexibility, all the default register values can be
overwritten using an optional MicrowireTM serial EEPROM.
To enhance device driver efficiency and reduce interrupt
latency, internal UARTs have multi-port features such as
shadowed FIFO fill levels, a global interrupt source register
and Good-Data Status, readable in four adjacent DWORD
registers visible to logical functions in IO space and
memory space.
Expansion of serial cards beyond four channels is possible
using the 8-bit pass-through Local Bus function. The
addressable space can be increased up to 256 bytes, and
divided into four chip-select regions. In 32-bit mode the bus
can map up to 16kb of Memory address space. This
flexible expansion scheme caters for cards with up to 20
serial ports using external 16C950, 16C952, 16C954 or
compatible devices, for composite applications such as
combined serial and parallel port expansion cards.
The OX16PCI954 also provides an IEEE1284 EPP parallel
port which fully supports the existing Centronics interface.
The parallel port can be enabled in place of the Local Bus.
Oxford Semiconductor Ltd.
69 Milton Park, Abingdon, Oxon, OX14 4RX, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
© Oxford Semiconductor 1999
OX16PCI954 Data Sheet Revision 1.3 – Feb. 1999
Part No. OX16PCI954-TQC60-A

1 page




OX16PCI954 pdf
OXFORD SEMICONDUCTOR LTD.
OX16PCI954
1 PERFORMANCE COMPARISON
Feature
Internal serial channels
Integral 1284 EPP parallel port
Multi-function PCI device
Support for PCI Power Management
Zero wait-state read/write operation
No. of available Local Bus interrupt pins
DWORD access to UART Interrupt Source
Registers & FIFO Levels
Good-Data status
Full Plug and Play with external EEPROM
Subsystem Vendor ID & Subsystem ID with
no external EEPROM
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Sleep mode
Auto Xon/Xoff flow
Auto CTS#/RTS# flow
Auto DSR#/DTR# flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmitter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Software reset
Device ID
9-bit data frames
RS485 buffer enable
Infra-red (IrDA)
OX16PCI954
4
yes
yes
yes
yes1
12
yes
yes
yes
yes
yes
15 Mbps
60 Mbps
128
yes
yes
yes
yes
128
128
128
yes
yes
yes
248
yes
yes
yes
yes
yes
yes
16C554 +
PLX9050
0
no
no
no
no
2
no
no
yes
no
no
115 Kbps
n/a
16
no
no
no
no
4
1
n/a
no
no
no
n/a
no
no
no
no
no
no
16C654 +
PLX9050
0
no
no
no
no
2
no
no
yes
no
no
1.5 Mbps
n/a
64
yes
yes
yes
no
4
4
4
no
no
no
2
no
no
no
no
no
yes
Table 1: OX16PCI950 performance compared with PLX + generic UART combinations
Note 1: Zero wait-state applies only to internal UARTs
Improvements of the OX16PCI954 over discrete solutions:
Higher degree of integration:
OX16PCI954 offers four internal 16C950 high-performance
UARTs and one bi-directional parallel port.
Improved access timing:
Access to internal UARTs require zero or one PCI wait
states. A PCI read transaction from an internal UART can
complete within five PCI clock cycles and a write
transaction to an internal UART can complete within four
PCI clock cycles.
Reduces interrupt latency:
OX16PCI954 offers shadowed FIFO levels and Interrupt
status registers of internal UARTs, and Interrupt Status of
internal UARTs and MIO pins to reduce the device driver
interrupt latency.
Data Sheet Revision 1.3
Page 5

5 Page





OX16PCI954 arduino
OXFORD SEMICONDUCTOR LTD.
OX16PCI954
Mode
Dir1 Name
00 01 10 11
Subsystem ID & Subsystem Vendor ID pins
N/A N/A I Sub_ID[15:0]
N/A N/A I Sub_V_ID[15:0]
Multi-purpose & External interrupt pins
131 N/A N/A 131 I/O MIO0
Description
Subsystem ID. After reset the subsystem ID of Function 0
will default to the value assigned to these pins
Subsystem Vendor ID. After reset the subsystem vendor ID
of Function 0 will default to the value assigned to these pins.
Multi-purpose I/O 0. Can drive high or low, or assert a PCI
interrupt
N/A 131 N/A N/A
130 130 N/A 130
Z Hi-Z
I/O MIO1
Permanent high impedance
Multi-purpose I/O 1. Can drive high or low, or assert a PCI
interrupt
Z Hi-Z
129 129 N/A 129 I/O MIO2
Permanent high-impedance when LCC[6:5] ‘00’
Multi-purpose I/O 2. When LCC[7] = 0, this pin can drive high
or low, or assert a PCI interrupt.
I PME_In
124-128
N/A 124-8, I/O MIO[3:11]
88-91
88-91
EEPROM pins
41 O EE_CK
39 O EE_CS
42 IU EE_DI
40
Miscellaneous pins
43
44,45
O EE_DO
IU TEST
I Mode[1:0]
Input power management event. When LCC[7] is set this
input pin can assert a function 1 PME#
Multi-purpose I/O pins. Can drive high or low, or assert a PCI
interrupt
EEPROM clock
EEPROM active-high Chip Select
EEPROM data in. When the serial EEPROM is connected,
this pin should be pulled up using 1-10k resistor. When the
EEPROM is not used the internal pullup is sufficient.
EEPROM data out.
Must be connected to GND
Mode selector:
00: Function 0 is Quad UART, Function 1 is 8-bit local bus
01: Function 0 is Quad UART, Function 1 is parallel port
10: Function 0 is Quad UART, Function 1 is unusable as the
local bus pins are used to assign Subsystem ID and
Subsystem Vendor ID to function 0
Power and ground2
18, 31, 57, 72, 97, 111, 147, 157
22, 65, 104, 137
8, 17, 25, 30, 35, 56, 70, 96, 110,
142, 146, 153, 158
21, 62, 103, 135
11: Function 0 is unusable, Function 1 is 32-bit local bus
V AC VDD
V DC VDD
G AC GND
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state
Supplies GND to output buffers in switching (AC) state
G DC GND
Ground (0 volts). Supplies GND to core logic, input buffers
and output buffers in steady state
Table 2: Pin Descriptions
Data Sheet Revision 1.3
Page 11

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