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PDF OXMPCI954 Data sheet ( Hoja de datos )
| Número de pieza | OXMPCI954 | |
| Descripción | Integrated High Performance Quad UARTs | |
| Fabricantes | Oxford Semiconductor | |
| Logotipo |  |
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FEATURES
• Software compatible with OX16PCI954
• Four 16C950 High performance UART channels
• 8-bit Pass-through Local Bus (PCI Bridge)
• IEEE1284 Compliant SPP/EPP/ECP parallel port (with
external transceiver)
• Efficient 32-bit, 33MHz, Multi-function target-only PCI
controller, fully compliant to PCI Local Bus specification 3.0,
and PCI Power Management Specification 1.1
• PCI and miniPCI Modes (with CLKRUN# and D3cold
support in miniPCI modes)
• UARTs fully software compatible with 16C550-type devices.
• UART operation up to 60 MHz via external clock source. Up
to 20MHz with the crystal oscillator.
• Baud rates up to 60Mbps in external 1x clock mode and
15Mbps in asynchronous mode.
• 128-byte deep FIFO per transmitter and receiver
• Flexible clock prescaler, from 1 to 31.875
• Automated in-band flow control using programmable
Xon/Xoff in both directions
DESCRIPTION
The OXmPCI954 is a single chip solution for PCI and mini-
PCI based serial and parallel expansion add-in cards. It is
a dual function PCI device, where function 0 offers four
ultra-high performance OX16C950 UARTs, and function 1
is configurable either as an 8-bit Local Bus or a bi-
directional parallel port.
Each UART channel in the OXmPCI954 is the fastest
available PC-compatible UART, offering data rates up to
15Mbps and 128-byte deep transmitter and receiver FIFOs.
The deep FIFOs reduce CPU overhead and allow
utilisation of higher data rates. Each UART channel is
software compatible with the widely used industry-standard
16C550 devices (and compatibles), as well as the
OX16C95x family of high performance UARTs. In addition
to increased performance and FIFO size, the UARTs also
provide the full set of OX16C95x enhanced features
including automated in-band flow control, readable FIFO
levels etc.
To enhance device driver efficiency and reduce interrupt
latency, internal UARTs have multi-port features such as
shadowed FIFO fill levels, a global interrupt source register
and Good-Data Status, readable in four adjacent DWORD
registers visible to logical functions in I/O space and
memory space.
Expansion of serial cards beyond four channels is possible
using the 8-bit pass-through Local Bus function. The
OXmPCI954 DATA SHEET
Integrated High Performance Quad UARTs,
8-bit Local Bus/Parallel Port.
3.3v PCI/miniPCI interface.
• Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
• Arbitrary trigger levels for receiver and transmitter FIFO
interrupts and automatic in-band and out-of-band flow
control
• Infra-red (IrDA) receiver and transmitter operation
• 9-bit data framing, as well as 5,6,7 and 8 bits
• Detection of bad data in the receiver FIFO
• Global Interrupt Status and readable FIFO levels to facilitate
implementation of efficient device drivers.
• Local registers to provide status/control of device functions.
• 12 multi-purpose I/O pins, which can be configured as input
interrupt pins or ‘wake-up’.
• Auto-detection of a wide range of optional MicrowireTM
compatible EEPROMs, to re-configure device parameters.
• Function access, to pre-configure each function prior to
handover to generic device drivers.
• Operation via IO or memory mapping.
• 3.3V operation (5v tolerance on selected I/Os)
• Extended Operating Temp. Range : -40C to 105C
• 160-pin LQFP or 176-pin VBGA package
addressable space can be increased up to 256 bytes, and
divided into four chip-select regions. This flexible
expansion scheme caters for cards with up to 20 serial
ports using external 16C950, 16C952, 16C954 or
compatible devices, or composite applications such as
combined serial and parallel port expansion cards. Serial
port cards with up to 20 ports (or with 4 serial ports and a
parallel port) can be designed without redefining any
device or timing parameters.
The parallel port is an IEEE 1284 compliant SPP/EPP/
ECP parallel port that fully supports the existing Centronics
interface. The parallel port can be enabled in place of the
Local Bus. An external bus transceiver is required for 5V
parallel port operation.
For applications that do not require the local bus, or the
parallel port, card designers can assign a Subsystem
Vendor ID and a Subsystem ID directly using 32 input pins.
For full flexibility, all the default configuration register
values can be overwritten using an optional MicrowireTM
compatible serial EEPROM. This EEPROM can also be
used to provide function access to pre-configure each
UART into enhanced modes or pre-configure devices on
the local bus/parallel port, prior to any PCI configuration
accesses and before control is handed to (generic) device
drivers.
Oxford Semiconductor Ltd.
External—Free Release
© Oxford Semiconductor 2005
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
OXmPCI954 DataSheet DS-0019 – June 2005
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
1 page  
OXFORD SEMICONDUCTOR LTD.
OXmPCI954
10.3 REGISTER DESCRIPTION............................................................................................................................................... 88
10.3.1 PARALLEL PORT DATA REGISTER ‘PDR’ ................................................................................................................. 88
10.3.2 ECP FIFO ADDRESS / RLE ......................................................................................................................................... 88
10.3.3 DEVICE STATUS REGISTER ‘DSR’ ............................................................................................................................ 88
10.3.4 DEVICE CONTROL REGISTER ‘DCR’......................................................................................................................... 89
10.3.5 EPP ADDRESS REGISTER ‘EPPA’ ............................................................................................................................. 89
10.3.6 EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................. 89
10.3.7 ECP DATA FIFO ........................................................................................................................................................... 89
10.3.8 TEST FIFO .................................................................................................................................................................... 89
10.3.9 CONFIGURATION A REGISTER ................................................................................................................................. 89
10.3.10 CONFIGURATION B REGISTER ................................................................................................................................. 89
10.3.11 EXTENDED CONTROL REGISTER ‘ECR’................................................................................................................... 90
11 SERIAL EEPROM ............................................................................................................................ 91
11.1 SPECIFICATION ............................................................................................................................................................... 91
11.1.1 ZONE 0: HEADER ........................................................................................................................................................ 92
11.1.2 ZONE 1: LOCAL CONFIGURATION REGISTERS....................................................................................................... 93
11.1.3 ZONE 2: IDENTIFICATION REGISTERS ..................................................................................................................... 94
11.1.4 ZONE 3: PCI CONFIGURATION REGISTERS ............................................................................................................ 94
11.1.5 ZONE 4 : POWER MANAGEMENT DATA (AND DATA_SCALE ZONE) ............................................................. 95
11.1.6 ZONE 5 : FUNCTION ACCESS .................................................................................................................................... 95
12 OPERATING CONDITIONS ............................................................................................................. 97
12.1 DC ELECTRICAL CHARACTERISTICS .......................................................................................................................... 97
13 AC ELECTRICAL CHARACTERISTICS.......................................................................................... 99
13.1 PCI BUS ............................................................................................................................................................................ 99
13.2 LOCAL BUS...................................................................................................................................................................... 99
13.3 SERIAL PORTS .............................................................................................................................................................. 101
14 TIMING WAVEFORMS................................................................................................................... 102
15 PACKAGE INFORMATION............................................................................................................ 117
15.1 160-PIN LQFP................................................................................................................................................................. 117
15.2 176-PIN VBGA ................................................................................................................................................................ 118
16 ORDERING INFORMATION .......................................................................................................... 119
DS-0019 Jun 05
External—Free Release
Page 5
5 Page 
OXFORD SEMICONDUCTOR LTD.
OXmPCI954
4.2 Enhanced Modes of Operation.
Mode ‘011’: Quad UARTs (Unique BARs) +
8-bit Local Bus
MODE[2:0] = 011
Mode ‘100’ QUAD UARTs + 8-BIT Local Bus.
MODE[2:0] = 100
LBA1
LBA0
LBRST
LBRST#
MIO7
MIO6
MIO5
MIO4
MIO3
MIO2
MIO1
MIO0
INTA#
INTB#/CLKRUN#
RST#
GND
CLK
PME#
AD31
AD30
AD29
GND
AD28
AD27
AD26
GND
AD25
AD24
C/BE3#
IDSEL
AD23
AD22
GND
VDD
AD21
AD20
AD19
VDD
GND
AD18
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
OXmPCI954-LQ-A
80 SOUT3
79 SOUT2
78 RTS2#
77 DTR2#
76 CTS2#
75 DSR2#
74 DCD2#
73 RI2#
72 VDD
71 UART_Ck_Out
70 GND
69 SIN2
68 SIN1
67 RI1#
66 DCD1#
65 VDD
64 XTLO
63 XTLI
62 GND
61 DSR1#
60 CTS1#
59 DTR1#
58 RTS1#
57 VDD
56 GND
55 SOUT1
54 SOUT0
53 RTS0#
52 DTR0#
51 CTS0#
50 DSR0#
49 DCD0#
48 RI0#
47 SIN0
46 FIFOSEL
45 Mode0
44 Mode1
43 Mode2
42 EE_DI
41 EE_CK
LBA1
LBA0
LBRST
LBRST#
MIO7
MIO6
MIO5
MIO4
MIO3
MIO2
MIO1
MIO0
INTA#
INTB#/CLKRUN#
RST#
GND
CLK
PME#
AD31
AD30
AD29
GND
AD28
AD27
AD26
GND
AD25
AD24
C/BE3#
IDSEL
AD23
AD22
GND
VDD
AD21
AD20
AD19
VDD
GND
AD18
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
OXmPCI954-LQ-A
80 SOUT3
79 SOUT2
78 RTS2#
77 DTR2#
76 CTS2#
75 DSR2#
74 DCD2#
73 RI2#
72 VDD
71 UART_Ck_Out
70 GND
69 SIN2
68 SIN1
67 RI1#
66 DCD1#
65 VDD
64 XTLO
63 XTLI
62 GND
61 DSR1#
60 CTS1#
59 DTR1#
58 RTS1#
57 VDD
56 GND
55 SOUT1
54 SOUT0
53 RTS0#
52 DTR0#
51 CTS0#
50 DSR0#
49 DCD0#
48 RI0#
47 SIN0
46 FIFOSEL
45 Mode0
44 Mode1
43 Mode2
42 EE_DI
41 EE_CK
Mode ‘101’ : QUAD UARTs + Parallel Port.
MODE[2:0] = 101
Mode ‘111’ : Standalone QUAD UART Mode
MODE[2:0] = 111
BUSY
PE
ACK#
NC
MIO7
MIO6
MIO5
MIO4
MIO3
MIO2
MIO1
NC
INTA#
INTB#/CLKRUN#
RST#
GND
CLK
PME#
AD31
AD30
AD29
GND
AD28
AD27
AD26
GND
AD25
AD24
C/BE3#
IDSEL
AD23
AD22
GND
VDD
AD21
AD20
AD19
VDD
GND
AD18
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
OXmPCI954-LQ-A
80 SOUT3
79 SOUT2
78 RTS2#
77 DTR2#
UART_addr(1)
UART_addr(0)
Read_Data_Control
NC
121
122
123
124
76 CTS2#
75 DSR2#
0 125
0 126
74 DCD2#
0 127
73 RI2#
0 128
72 VDD
0 129
71 UART_Ck_Out
0 130
70 GND
0 131
69 SIN2
0 132
68 SIN1
Uart_Interrupt
133
67 RI1#
0 134
66 DCD1#
RST#
135
65 VDD
GND
136
64 XTLO
Buffered_CLK
137
63 XTLI
0 138
62 GND
0 139
61 DSR1#
0 140
60 CTS1#
0 141
59 DTR1#
GND
142
58 RTS1#
0 143
57 VDD
0 144
56 GND
0 145
55 SOUT1
GND
146
54 SOUT0
53 RTS0#
52 DTR0#
51 CTS0#
50 DSR0#
49 DCD0#
48 RI0#
47 SIN0
46 FIFOSEL
45 Mode0
44 Mode1
43 TEST
42 EE_DI
41 EE_CK
0
0
1
0
0
0
GND
VDD
0
0
0
VDD
GND
0
147
148
149
150
151
152
153
154
155
156
157
158
159
160
OXmPCI954-LQ-A
80 SOUT3
79 SOUT2
78 RTS2#
77 DTR2#
76 CTS2#
75 DSR2#
74 DCD2#
73 RI2#
72 VDD
71 NC
70 GND
69 SIN2
68 SIN1
67 RI1#
66 DCD1#
65 VDD
64 XTLO
63 XTLI
62 GND
61 DSR1#
60 CTS1#
59 DTR1#
58 RTS1#
57 VDD
56 GND
55 SOUT1
54 SOUT0
53 RTS0#
52 DTR0#
51 CTS0#
50 DSR0#
49 DCD0#
48 RI0#
47 SIN0
46 FIFOSEL
45 Mode0
44 Mode1
43 Mode2
42 1
41 NC
9 NC. Do not connect these pins:
108,111,112,113,114,115,116,124,132
13 NC. Do not connect these pins:
39,40,41,71,102,104,105,106,107,108,111,112,124
DS-0019 Jun 05
External—Free Release
Page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet OXMPCI954.PDF ] | |
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