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PDF ATA6824 Data sheet ( Hoja de datos )
| Número de pieza | ATA6824 | |
| Descripción | High Temperature H-Bridge Motor Driver | |
| Fabricantes | ATMEL Corporation | |
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Features
• PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors
• High Temperature Capability up to 200° C Junction
• A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge
• Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply
the Gate of the External Battery Reverse Protection NMOS
• 5V/3.3V Regulator and Current Limitation Function
• Reset Derived From 5V/3.3V Regulator Output Voltage
• A Programmable Window Watchdog
• Battery Overvoltage Protection and Battery Undervoltage Management
• Overtemperature Warning and Protection (Shutdown)
• High Voltage Serial Interface for Communication
• QFN32 Package
1. Description
The ATA6824 is designed for high temperature mechatronic applications, for example
turbo chargers, where the electronic is mounted very close to the hot engine. In such
harsch environments the ICs have to withstand temperatures up to 150° C ambient
which results in junction temperatures up to 200° C. The IC is used to drive a continu-
ous current motor in a full H-bridge configuration. An external microcontroller controls
the driving function of the IC by providing a PWM signal and a direction signal and
allows the use of the IC in a motor-control application. The PWM control is performed
by the low-side switch; the high-side switch is permanently on in the driving phase.
The VMODE configuration pin can be set to 5V or 3.3V mode (for regulator and inter-
face high level). The window watchdog has a programmable time, programmable by
choosing a certain value of the external watchdog resistor RWD, internally trimmed to
an accuracy of 10%. To communicate with a host controller there is a HV Serial Inter-
face integrated.
High
Temperature
H-bridge Motor
Driver
ATA6824
Preliminary
DataSheet4 U .com
4931C–AUTO–09/06
1 page  
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ATA6824 [Preliminary]
4. Application
4.1 General Remark
This chapter describes the principal application for which the ATA6824 was designed. Because
Atmel cannot be considered to understand fully all aspects of the system, application and envi-
ronment, no warranties of fitness for a particular purpose are given.
Table 4-1. Typical External Components
Component Function
CVINT
CVCC
CCC
RCC
CVG
CCP
CVRES
RRWD
CSIO
Blocking capacitor at VINT
Blocking capacitor at VCC
Cross conduction time definition capacitor
Cross conduction time definition resistor
Blocking capacitor at VG
Charge pump capacitor
Reservoir capacitor
Watchdog time definition resistor
Filter capacitor for serial interface
Value
220 nF, 10V, X7R
2.2 µF, 10V, X7R
Typical 330 pF, 100V, COG
Typical 10 kΩ
470 nF, 25V, X7R
220 nF, 25V, X7R
470 nF, 25V, X7R
Typical 51 kΩ
Typical 220 pF, 100V
Tolerance
10%
10%
10%
10%
10%
1%
10%
5. Functional Description
5.1 Power Supply Unit with Supervisor Functions
5.1.1
Power Supply
The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper
external protection circuitry has to be added. It is recommended to use at least a capacitor com-
bination of storage and HF caps behind the reverse protection circuitry and closed to the VBAT
pin of the IC (see Figure 1-1 on page 2).
A fully-internal low-power and low-drop regulator, stabilized by an external blocking capacitor
provides the necessary low-voltage supply needed for the wake-up process. The low-power
band gap reference is trimmed and is used for the bigger VCC regulator, too. All internal blocks
are supplied by the internal regulator.
Note: The internal supply voltage VINT must not be used for any other supply purpose!
Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V
VCC regulator.
A power-good comparator checks the output voltage of the VINT regulator and keeps the whole
chip in reset as long as the voltage is too low.
There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for mea-
surement purposes. This switch is switched ON for VCC = HIGH and stays ON in case of a
watchdog reset. The signal can be used to switch on external voltage regulators, etc.
4931C–AUTO–09/06
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ATA6824 [Preliminary]
5.6 VG Regulator
The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage
will be used as one input for the charge pump, which generates the gate voltage for the
high-side driver. The purpose of the regulator is to limit the gate voltage for the external power
MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage
is reduced if the supply voltage at VBAT falls below 12V.
5.7 Charge Pump
The integrated charge pump is needed to supply the gates of the external power MOS transis-
tors. It needs a shuffle capacitor of 220 nF and a reservoir capacitor of 470 nF. Without load, the
output voltage on the reservoir capacitor is VBAT plus VG. The charge pump is clocked with a
dedicated internal oscillator of 100 KHz. The charge pump is designed to reach a good EMC
level.
5.8 Thermal Shutdown
There is a thermal shutdown block implemented. With rising junction temperature, a first warning
level will be reached at 180°C. At this point the IC stays fully functional and a warning will be
sent to the microcontroller. At junction temperature 200°C the VCC regulator will be switched off
and a reset occurs.
5.9 H-bridge Driver
The IC includes two push-pull drivers for control of two external power NMOS used as high-side
drivers and two push-pull drivers for control of two external power NMOS used as low-side driv-
ers. The drivers are able to be used with standard and logic-level power NMOS.
The drivers for the high-side control use the charge pump voltage to supply the gates with a volt-
age of VG above the battery voltage level. The low-side drivers are supplied by VG directly. It is
possible to control the external load (motor) in the forward and reverse direction (see Table 5-1
on page 10). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible in
both directions.
5.9.1
Cross Conduction Time
To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the exter-
nal power NMOS is realized. An external RC combination defines the cross conduction time in
the following way:
tCC (µs) = 0.41 × RCC (kΩ) × CCC (nF) (tolerance: ±5% ±0.15 µs)
The RC combination is charged to 5V and the switching level of the internal comparator is 67%
of the start level.
The resistor RCC must be greater than 5 kΩ and should be as close as possible to 10 kΩ, the CCC
value has to be ≤5 nF. Use of COG capacitor material is recommended.
The time measurement is triggered by the PWM or DIR signal crossing the 50% level.
4931C–AUTO–09/06
DataSheet4 U .com
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| PDF Descargar | [ Datasheet ATA6824.PDF ] | |
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