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56F8023 데이터시트 PDF




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부품번호 56F8023 기능
기능 16-bit Digital Signal Controllers
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56F8023 데이터시트, 핀배열, 회로
56F8033/56F8023
Data Sheet
Technical Data
56F8000
16-bit Digital Signal Controllers
MC56F8023
Rev. 6
02/2010
freescale.com




56F8023 pdf, 반도체, 판매, 대치품
56F8033/56F8023 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 56F8033 offers 64KB (32K x 16) Program Flash
• 56F8023 offers 32KB (16K x 16) Program Flash
• 56F8033 offers 8KB (4K x 16) Unified Data/Program
RAM
• 56F8023 offers 4KB (2K x 16) Unified Data/Program
RAM
• One 6-channel PWM module
• Two 3-channel 12-bit Analog-to-Digital Converters
(ADCs)
• Two Internal 12-bit Digital-to-Analog Converters
(DACs)
• Two Analog Comparators
• One Programmable Interval Timer (PIT)
• One Queued Serial Communication Interface (QSCI)
with LIN slave functionality
• One Queued Serial Peripheral Interfaces (QSPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I2C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
RESET or
GPIOA
4
VCAP
VDD
VSS
2
VDDA VSSA
5 PWM
or TMRA or GPIOA
JTAG/EOnCE
Port or
GPIOD
Digital Reg Analog Reg
16-Bit
56800E Core
Low-Voltage
Supervisor
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
DAC
4 AD0
ADC
or CMP
or GPIOC
4 AD1
Memory
Program Memory
16K x 16 Flash
32K x 16 Flash
Unified Data /
Program RAM
2K x 16
4K x 16
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
Programmable
Interval
Timer
IPBus Bridge (IPBB)
I2C
or CMP
or GPIOB
QSPI
or PWM
or I2C
or TMRA
or GPIOB
QSCI
or PWM
or I2C
or TMRA
or GPIOB
24
2
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
Clock
Generator*
O
S
C
*Includes On-Chip
Relaxation Oscillator
56F8033/56F8023 Block Diagram
56F8033/56F8023 Data Sheet, Rev. 6
4 Freescale Semiconductor

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56F8023 전자부품, 판매, 대치품
56F8033/56F8023 Features
1.1.4 Peripheral Circuits for 56F8033/56F8023
• One multi-function six-output Pulse Width Modulator (PWM) module
— Up to 96MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and edge-aligned PWM signal mode
— Four programmable fault inputs with programmable digital filter
— Double-buffered PWM registers
— Each complementary PWM signal pair allows selection of a PWM supply source from:
– PWM generator
– External GPIO
– Internal timers
– Analog comparator outputs
– ADC conversion result which compares with values of ADC high- and low-limit registers to set
PWM output
• Two independent 12-bit Analog-to-Digital Converters (ADCs)
— 2 x 3 channel inputs
— Supports both simultaneous and sequential conversions
— ADC conversions can be synchronized by both PWM and timer modules
— Sampling rate up to 2.67MSPS
— 16-word result buffer registers
• Two internal 12-bit Digital-to-Analog Converters (DACs)
— 2 μs settling time when output swing from rail to rail
— Automatic waveform generation generates square, triangle and sawtooth waveforms with
programmable period, update rate, and range
• One 16-bit multi-purpose Quad Timer module (TMR)
— Up to 96MHz operating clock
— Eight independent 16-bit counter/timers with cascading capability
— Each timer has capture and compare capability
— Up to 12 operating modes
• One Queued Serial Communication Interface (QSCI) with LIN Slave functionality
— Full-duplex or single-wire operation
— Two receiver wake-up methods:
– Idle line
– Address mark
— Four-bytes-deep FIFOs are available on both transmitter and receiver
• One Queued Serial Peripheral Interfaces (QSPI)
— Full-duplex operation
Freescale Semiconductor
56F8033/56F8023 Data Sheet, Rev. 6
7

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