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PDF PCM3052A Data sheet ( Hoja de datos )

Número de pieza PCM3052A
Descripción STEREO AUDIO CODEC
Fabricantes Burr-Brown 
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BurrĆBrown Products
from Texas Instruments
PCM3052A
SLES160 – NOVEMBER 2005
24-BIT, 96-kHz STEREO AUDIO CODEC WITH
MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA
FEATURES
Microphone Amplifier and Bias
– Monaural Microphone Amplifier: 34-dB Gain
at Differential Input
– Microphone Bias: 1 mA at 3.75 V
Multiplexer and PGA
– Multiplex of Stereo Single-Ended Line
Inputs and Monaural Microphone Amplifier
– 0.1 Vrms to 1.5 Vrms Full-Scale Input Range
– 22-kInput Resistance at 0.1-Vrms Input
– 20 dB to –4 dB/range, 1 dB/step PGA
Reference Output: ±10 mA at 2.5 V
24-Bit Delta-Sigma ADC and DAC
Stereo ADC:
– Full-Scale Input: 3 Vp-p
– Antialiasing Filter Included
– 1/64 Decimation Filter:
Pass-Band Ripple: ±0.05 dB
Stop-Band Attenuation: –65 dB
– On-Chip High-Pass Filter: 0.91 Hz at
fS = 48 kHz
– High Performance:
THD+N: –94 dB (Typical)
SNR: 101 dB (Typical)
Dynamic Range: 101 dB (Typical)
Stereo DAC:
– Single-Ended Voltage Output: 4 Vp-p
– Analog Low-Pass Filter Included
×8 Oversampling Digital Filter:
Pass-Band Ripple: ±0.03 dB
Stop-Band Attenuation: –50 dB
– High Performance:
THD+N: –97 dB (Typical)
SNR: 105 dB (Typical)
Dynamic Range: 104 dB (Typical)
S/PDIF Output for DAC Digital Input
A
Multiple Functions With I2C Interface:
– Digital De-Emphasis: 32-, 44.1-, 48-kHz
– Zipper-Noise-Free Digital Attenuation and
Soft Mute for DAC
– HPF Bypass Control for ADC
– S/PDIF Output Control
– Power Down: ADC/DAC Independently
External Power-Down Pin:
– ADC/DAC Simultaneously
Audio Data Format: 24-Bit I2S Only
Sampling Rate:
– 16–96 kHz for Both ADC and DAC
System Clock: 256 fS Only
Dual Power Supplies:
– 5 V for Analog and 3.3 V for Digital
Package: VQFN-32
DESCRIPTION
The PCM3052A is a low-cost, single-chip, 24-bit
stereo audio codec (ADC and DAC) with
single-ended analog voltage input and output. It also
has an analog front end consisting of a 34-dB
microphone amplifier, microphone bias generator, 2
stereo multiplexers, and a wide-range PGA. Analog-
to-digital converters (ADCs) employ delta-sigma
modulation with 64-times oversampling. On the other
hand, digital-to-analog converters (DACs) employ
modulation with 64- and 128-times oversampling.
ADCs include a digital decimation filter with a
high-pass filter, and DACs include an 8-times
oversampling digital interpolation filter. The
PCM3052A has many functions which are controlled
using the I2C interface: DAC digital de-emphasis,
digital attenuation, soft mute etc. The PCM3052A
also has an S/PDIF output pin for the DAC digital
input. The power-down mode, which works on ADCs
and DACs simultaneously, is provided by an external
pin. The PCM3052A is suitable for a wide variety of
cost-sensitive PC audio (recorder and player)
applications where good performance is required.
The PCM3052A is fabricated using a highly advanced
CMOS process and is available in a small 32-pin
VQFN package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated

1 page




PCM3052A pdf
PCM3052A
www.ti.com
SLES160 – NOVEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless
otherwise noted
PARAMETER
Dynamic Performance (8)
THD+N Total harmonic distortion + noise
Dynamic range
S/N Signal-to-noise ratio
Channel separation
Analog Output
Output voltage
Center voltage
Load impedance
LPF frequency response
Digital Filter Performance
Pass band
Stop band
Pass-band ripple
Stop-band attenuation
Delay time
De-emphasis error
POWER SUPPLY REQUIREMENTS
VCC1
VCC2
VCC3
VDD
Voltage range
ICC (9)
IDD
Supply current
Power dissipation
TEST CONDITIONS
fS = 48 kHz, VOUT = 0 dB
fS = 96 kHz, VOUT = 0 dB
fS = 48 kHz, VOUT = –60 dB
fS = 96 kHz, VOUT = –60 dB
fS = 48 kHz, EIAJ, A-weighted
fS = 96 kHz, EIAJ, A-weighted
fS = 48 kHz, EIAJ, A-weighted
fS = 96 kHz, EIAJ, A-weighted
fS = 48 kHz
fS = 96 kHz
AC coupling
f = 20 kHz
f = 40 kHz
±0.03 dB
0.546 fS
MIN TYP MAX UNIT
–97 –90
–99
dB
–42
–43
98 104
106
dB
99 105
106
dB
97 103
104
dB
0.8 VCC2
0.5 VCC2
5
–0.03
–0.20
Vp-p
V
k
dB
0.546 fS
–50
0.454 fS
±0.03
20/fS
±0.1
Hz
Hz
dB
dB
s
dB
fS = 48 kHz
fS = 96 kHz
Full power down (10)
fS = 48 kHz
fS = 96 kHz
Full power down(10)
Operation, fS = 48 kHz
Operation, fS = 96 kHz
ADC operation at fS = 48
kHz/DAC power down
ADC power down/DAC operation
at fS = 48 kHz
Full power down(10)
4.25 5 5.5
VDC
3 3.3 3.6
39 50
mA
41
300 µA
10 15
mA
19
90 µA
228 300
268
180 mW
63
1.8
(8) fOUT = 1 kHz, using System Two audio measurement system by Audio Precision in the RMS mode with 20-kHz LPF and 400-Hz HPF.
(9) ICC = ICC1 + ICC2 + ICC3
(10) Halt SCKI, BCK, LRCK.
5

5 Page





PCM3052A arduino
PCM3052A
www.ti.com
SLES160 – NOVEMBER 2005
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION)
All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless
otherwise noted.
DIGITAL FILTER
FREQUENCY RESPONSE, STOP BAND (Sharp Rolloff)
0
FREQUENCY RESPONSE, PASS BAND (Sharp Rolloff)
0.2
−20
−40
−60
−80
−100
−120
0.0
−0.2
−0.4
−0.6
−0.8
−140
0
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0
123
Frequency [×fS]
Figure 9.
DE-EMPHASIS (fS = 32 kHz)
4
G009
2 4 6 8 10 12 14
f − Frequency − kHz
G011
Figure 11.
−1.0
0.0
0.5
0.4
0.3
0.2
0.1
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
0.1 0.2 0.3 0.4
Frequency [×fS]
Figure 10.
DE-EMPHASIS ERROR (fS = 32 kHz)
0.5
G010
2 4 6 8 10 12 14
f − Frequency − kHz
G012
Figure 12.
11

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