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부품번호 | NB4L339 기능 |
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기능 | 2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan-Out Buffer | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 12 페이지수
NB4L339
2.5 V / 3.3 V Differential 2:1
Clock IN to Differential
LVPECL Clock Generator /
Divider / Fan-Out Buffer
Multi−Level Inputs w/ Internal Termination
Description
The NB4L339 is a multi−function Clock generator featuring a 2:1
Clock multiplexer front end and simultaneously outputs a selection of
four different divide ratios from its four divider blocks; ÷1/÷2/÷4/÷8.
One divide block has a choice of ÷1 or ÷ 2.
The output of each divider block is fanned−out to two identical
differential LVPECL copies of the selected clock. All outputs provide
standard LVPECL voltage levels when externally terminated with a
50−ohm resistor to VCC − 2 V.
The differential Clock inputs incorporate internal 50−W termination
resistors and will accept LVPECL, CML or LVDS logic levels.
The common Output Enable pin (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the internal clock
is in the LOW state. This avoids any chance of generating a runt clock
pulse on the internal clock when the device is enabled/disabled as can
happen with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal divider stages. The
internal enable flip−flop is clocked on the falling edge of the input
clock. Therefore, all associated specification limits are referenced to
the negative edge of the clock input.
This device is housed in a 5x5 mm 32 pin QFN package.
Features
• Maximum Input/Output Clock Frequency > 700 MHz
• Low Skew LVPECL Outputs, 15 ps typical
• 1 ns Typical Propagation Delay
• 150 ps Typical Rise and Fall Times
• 0.15 ps Typical RMS Phase Jitter
• 0.5 ps Typical RMS Random Clock Period Jitter
• LVPECL, CML or LVDS Input Compatible
• Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V
• LVPECL Output Level; 750 mV Peak−to−Peak, Typical
• Internal 50−W Input Termination Provided
• Synchronous Output Enable/Disable
• Asynchronous Master Reset
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• −40°C to 85°C Ambient Operating Temperature
• 32−Pin QFN, 5 mm x 5 mm
• This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 3
1
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MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB4L339
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
Figure 1. Simplified Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
Publication Order Number:
NB4L339/D
NB4L339
Table 5. ATTRIBUTES
Characteristics
Input Default State Resistors
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity (Note 2)
QFN−32
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Value
80 kW
> 2.0 kV
> 100 V
Level 1
UL 94 V−0 @ 0.125 in
366
Table 6. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
VIO
VINPP
IIN
Positive Power Supply
Input/Output Voltage
Differential Input Voltage Swing
|CLK − CLK|
Input Current Through RT (50 W Resistor)
VEE = 0 V
VEE = 0 V
Static
Surge
−0.5 = VIo ≤ VCC + 0.5
4.0
4.0
2.8
45
80
V
V
V
mA
IOUT
Output Current
Continuous
Surge
50 mA
100
TA Operating Temperature Range
QFN−32
Tstg Storage Temperature Range
qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 LFPM
500 LFPM
QFN−32
QFN−32
−40 to +85
−65 to +150
31
27
°C
°C
°C/W
qJC Thermal Resistance (Junction−to−Case)
(Note 3)
QFN−32
12 °C/W
Tsol Wave Solder (Pb−Free)
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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4페이지 NB4L339
Figure 4. NB4L339 vs. Agilent 8665A 622.08 MHz at 3.3 V, Room Ambient
800
700
600
500
400
300
200
100
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
fout, CLOCK OUTPUT FREQUENCY (GHz)
Figure 5. Output Voltage Amplitude (VOUTPP) vs. Input Clock Frequency (fin) at
Ambient Temperature (Typical)
Application Information
The NB4L339 is a high−speed, Clock multiplexer, divider
and low skew fan−out buffer featuring a 2:1 Clock
multiplexer front end and outputs a selection of four
different divide ratios; ÷1/2/4/8. One divide block has a
choice of ÷1 or ÷ 2. The outputs of all four divider blocks are
fanned−out to two pair of identical differential LVPECL
copies of the selected clock. All outputs provide standard
LVPECL voltage levels when externally terminated with a
50−ohm resistor to VTT = VCC − 2 V.
The differential Clock input buffers incorporate internal
50−W termination resistors in a 100−W center−tapped
configuration and are accessible via a VTx pin. This feature
provides transmission line termination on−chip, at the
receiver end, eliminating external components. Inputs
CLKA/B and CLKA/B must be signal driven or auto
oscillation may result.
The NB4L339 Clock inputs can be driven by a variety of
differential signal level technologies including LVDS,
LVPECL, or CML.
The internal dividers are synchronous to each other.
Therefore, the common output edges are precisely aligned.
The Output Enable pin (EN) is synchronous so that the
internal divider flip−flops will only be enabled/disabled
when the internal clock is in the LOW state. This avoids any
chance of generating a runt pulse on the internal clock when
the device is enabled/disabled, as can happen with an
asynchronous control. The internal enable flip−flop is
clocked on the falling edge of the input clock. Therefore, all
associated specification limits are referenced to the negative
edge of the clock input.
The Master Reset (MR) is asynchronous. When MR is
forced LOW, all Q outputs go to logic LOW.
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부품번호 | 상세설명 및 기능 | 제조사 |
NB4L339 | 2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan-Out Buffer | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |