PDF ADIS16204 Data sheet ( Hoja de datos )

Número de pieza	ADIS16204
Descripción	Programmable Dual Axis Digital Accelerometer and Impact Sensor
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com Preliminary Technical Data Programmable Dual Axis Digital Accelerometer and Impact Sensor ADIS16204 FEATURES Dual-axis impact sensing Dual-axis acceleration sensing, +70g, +35g 14-bit resolution 17.1 mg/LSB, 8.55mg/LSB sensitivity Impact peak-level sample and hold Programmable Event Recorder 400Hz double-pole Bessel sensor response 12-bit digital temperature sensor output Digitally controlled sensitivity and bias Digitally controlled sample rate, up to 4096 SPS Dual alarm settings with programmable threshold limits Auxiliary digital I/O Digitally activated self test Digitally activated low power mode SPI®-compatible serial interface Auxiliary 12-bit ADC input and DAC output Single-supply operation: 3.0 V to +3.6 V 3500 g powered shock survivability APPLICATIONS Impact detection Condition monitoring Safety Systems Shock sensor GENERAL DESCRIPTION The ADIS16204 is a programmable impact sensor in a single compact package enabled by the Analog Devices iSensor™ integration. By enhancing the Analog Devices iMEMS® sensor technology with an embedded signal processing solution, the ADIS16204 provides tunable digital sensor data in a convenient format that can be accessed using a serial peripheral interface (SPI). The SPI interface provides access to measurements for dual-axis linear acceleration, a root-sum-square (RSS) of both axes, temperature, power supply, and one auxiliary analog input. Easy access to digital sensor data provides developers with a system-ready device, reducing development time, cost, and program risk. Unique characteristics of the end system are accommodated easily through several built-in features, such as a single command in-system offset calibration, along with convenient sample rate control. Rev. PrA 10/10/2006 4:24 AM Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. FUNCTIONAL BLOCK DIAGRAM AUX AUX ADC DAC VREF Temperature Sensor Inertial MEMS Sensor Self-Test Signal Conditioning & Conversion Digital Processing Digital Control SPI Port VDD COM Power Management Alarms Aux I/O RST DIO0 DIO1 Figure 1. CS SCLK DIN DOUT The ADIS16204 offers the following embedded features, which eliminate the need for external circuitry and provide a simplified system interface: • Peak sample and hold • Programmable Event Recording • Configurable trigger levels • Auxiliary 12-bit ADC and DAC • Configurable digital I/O port • Digital self-test function The ADIS16204 offers two power management features for managing system-level power dissipation: low power mode and a configurable shutdown feature. The ADIS16204 is available in a 9.2 mm × 9.2 mm × 3.9 mm laminate-based land grid array (LGA) package with a temperature range of −40°C to +105°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. DataSheet4 U .com 1 page www.DataSheet4U.com Preliminary Technical Data TIMING SPECIFICATIONS TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted. Table 2. Parameter Description fSCLK tDATARATE tDATARATE tcs tDAV tDSU tDHD tDF tDR tSFS Fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz) Normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz) Chip select period, fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz) Chip select period, normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz) Chip select to clock edge Data output valid after SCLK edge Data input setup time before SCLK rising edge Data input hold time after SCLK rising edge Data output fall time Data output rise time CS high after SCLK edge 1 Guaranteed by design, not tested. Min1 0.01 0.01 40 100 48.8 24.4 48.8 5 TIMING DIAGRAMS CS SCLK tDATA RATE tSTALL tSTALL = tDATA RATE – 16/fSCLK Figure 2. SPI Chip Select Timing ADIS16204 Typ Max Unit 2.5 MHz 1.0 MHz μs μs ns 100 ns ns ns 5 12.5 ns min 5 12.5 ns min ns typ CS SCLK DOUT DIN tCS 1 MSB W/R 23 4 56 tDAV DB14 tDSU DB13 DB12 tDHD DB11 DB10 A5 A4 A3 A2 15 16 tSFS DB2 DB1 LSB D2 D1 LSB Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1) DataSheet4 U .com Rev. PrA \| Page 5 of 9 5 Page

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