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부품번호 | PDU54 기능 |
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기능 | ECL-INTERFACED PROGRAMMABLE DELAY LINE | ||
제조업체 | Data Delay Devices | ||
로고 | |||
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www.DataSheet4U.com
4-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU54)
PDU54
ddaeltaay 3
devices, inc.
FEATURES
• Digitally programmable in 16 delay steps
N/C
N/C
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully 100K-ECL interfaced & buffered
GND
N/C
N/C
N/C
• Available in 24-pin DIP (600 mil) socket or SMD
N/C
N/C
GND
OUT
PDU54-xx DIP
N/C
PDU54-xxM Military DIP N/C
1
2
3
4
5
6
7
8
9
10
11
12
PACKAGES
24 IN
23 N/C
22 VEE
21 A3
20 N/C
19 N/C
18 A2
17 A1
16 VEE
15 A0
14 N/C
13 N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
GND
OUT
N/C
N/C
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
IN
N/C
VEE
A3
N/C
N/C
A2
A1
VEE
A0
N/C
N/C
PDU54-xxC4 SMD
PDU54-xxMC4 Mil SMD
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU54-series device is a 4-bit digitally programmable delay line. The
delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the
address code (A3-A0) according to the following formula:
TDA = TD0 + TINC * A
IN Signal Input
OUT Signal Output
A3-A0 Address Bits
VEE -5 Volts
GND Ground
where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of
the device. The incremental delay is specified by the dash number of the device and can range from
100ps through 3000ps, inclusively. The address is not latched and must remain asserted during normal
operation.
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 40ps,
whichever is greater
• Inherent delay (TD0): 3.3ns typical
• Address to input setup (TAIS): 2.9ns
• Operating temperature: 0° to 85° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VEE: -5VDC ± 0.7V
• Power Supply Current: -300ma typical (50Ω to -2V)
• Minimum pulse width: 3ns or 10% of total delay,
whichever is greater
• Minimum period: 8ns or 2 x pulse width, whichever
is greater
A3-A0
IN
OUT
A i-1
PWIN
TDA
PW OUT
TOAX
TAIS
Ai
DASH NUMBER SPECIFICATIONS
Part
Number
PDU54-100
PDU54-200
PDU54-250
PDU54-400
PDU54-500
PDU54-750
PDU54-1000
PDU54-1200
PDU54-1500
PDU54-2000
PDU54-2500
PDU54-3000
Incremental Delay
Per Step (ps)
100 ± 50
200 ± 60
250 ± 60
400 ± 80
500 ± 100
750 ± 100
1000 ± 200
1200 ± 200
1500 ± 200
2000 ± 400
2500 ± 400
3000 ± 500
Total Delay
Change (ns)
1.50
3.00
3.75
6.00
7.50
11.25
15.00
18.00
22.50
30.00
37.50
45.00
NOTE: Any dash number between 100 and 3000
not shown is also available.
Figure 1: Timing Diagram
1997 Data Delay Devices
Doc #98004
3/18/98
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU54
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): -4.5V ± 0.1V
Input Pulse:
Standard 100K ECL
levels
Source Impedance: 50Ω Max.
Rise/Fall Time:
1.0 ns Max. (measured
between 20% and 80%)
Pulse Width:
Period:
PWIN = 10ns
PERIN = 100ns
OUTPUT:
Load:
Cload:
Threshold:
50Ω to -2V
5pf ± 10%
(VOH + VOL) / 2
(Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PULSE
GENERATOR
OUT
TRIG
IN DEVICE UNDER OUT
TEST (DUT)
REF
IN
TRIG
OSCILLOSCOPE
ADDRESS SELECT
Test Setup
INPUT
SIGNAL
OUTPUT
SIGNAL
TRISE
PWIN
PERIN
TFALL
80% VIH 80%
50% 50%
20% 20%
VIL
TRISE
TFALL
50%
VOH
50%
Timing Diagram For Testing
VOL
Doc #98004
3/18/98
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
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PDU54 | ECL-INTERFACED PROGRAMMABLE DELAY LINE | Data Delay Devices |
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