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PDF HY62LF16804A Data sheet ( Hoja de datos )

Número de pieza HY62LF16804A
Descripción 512Kx16bit full CMOS SRAM
Fabricantes Hynix 
Logotipo Hynix Logotipo



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Document Title
512K x16 bit 2.5V Super Low Power Full CMOS slow SRAM
Revision History
Revision No History
04 Initial Revision History Insert
Revised
- Reliability Spec Deleted
05 Change AC Characteristics
- tCLZ : 10/10/20 ---> 10/10/10
- tBLZ : 5/5/5 ---> 10/10/10
06 Part Number is changed
- HY62LF16803A --> HY62LF16804A
07 Marking Instruction is inserted
08 Test Condition Changed
- ILO / ISB / ISB1 / VDR / ICCDR
Marking Istruction Inserted
09 Change Logo
- Hyundai à Hynix
10 Change DC Parameter
- Isb1(LL) : 30uA à 25uA
- Isb1(Typ) : 8uA à 1uA
- Icc1(1us) : 5mA à 4mA
Change Data Retention
- IccDR(LL) : 25uA à 15uA
Change AC Parameter
- tOE
: 40ns à 35ns@70ns
HY62LF16804A Series
512Kx16bit full CMOS SRAM
Draft Date
Jul.02.2000
Remark
Preliminary
Oct.23.2000 Preliminary
Nov.13.2000 Preliminary
Dec.5.2000 Preliminary
Dec.16.2000 Preliminary
Apr.28.2001
Jan.28.2002
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.10/Jan. 2002
Hynix Semiconductor

1 page




HY62LF16804A pdf
HY62LF16804A Series
AC CHARACTERISTICS
Vcc = 2.3V~2.7V, TA= 0°C to 70°C/ -40°C to 85°C, unless otherwise specified
# Symbol Parameter
-70 -85
Min. Max. Min. Max.
READ CYCLE
1 tRC
Read Cycle Time
70 - 85 -
2 tAA
Address Access Time
- 70 - 85
3 tACS
Chip Select Access Time
- 70 - 85
4 tOE
Output Enable to Output Valid
- 35 - 45
5 tBA
/LB, /UB Access Time
- 70 - 85
6 tCLZ
Chip Select to Output in Low Z
10 - 10 -
7 tOLZ
Output Enable to Output in Low Z
5-5-
8 tBLZ
/LB, /UB Enable to Output in Low Z
10
-
10
-
9 tCHZ
Chip Deselection to Output in High Z
0
30
0
30
10 tOHZ Out Disable to Output in High Z
0 30 0 30
11 tBHZ /LB, /UB Disable to Output in High Z 0 30 0 30
12 tOH
Output Hold from Address Change
10 - 10 -
WRITE CYCLE
13 tWC
Write Cycle Time
70 - 85 -
14 tCW
Chip Selection to End of Write
60 - 70 -
15 tAW
Address Valid to End of Write
60 - 70 -
16 tBW
/LB, /UB Valid to End of Write
60 - 70 -
17 tAS
Address Set-up Time
0-0-
18 tWP
Write Pulse Width
50 - 55 -
19 tWR
Write Recovery Time
0-0-
20 tWHZ Write to Output in High Z
0 25 0 30
21 tDW
Data to Write Time Overlap
30 - 35 -
22 tDH
Data Hold from Write Time
0-0-
23 tOW
Output Active from End of Write
5-5-
-10
Min Max.
100 -
- 100
- 100
- 50
- 100
10 -
5-
10 -
0 30
0 30
0 30
15 -
100 -
80 -
80 -
80 -
0-
75 -
0-
0 35
45 -
0-
10 -
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
TA= 0°C to 70°C(Commercial)/ -40°C to 85°C, unless otherwise specified
PARAMETER
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.1V
Output Load
tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
Other
CL = 5pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
VTM = 2.3V
D
OUT
3067 Ohm
CL(1)
3345 Ohm
Note
1. Including jig and scope capacitance
Rev.10 /Jan. 2002
4

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