PDF PCA9537 Data sheet ( Hoja de datos )

Número de pieza	PCA9537
Descripción	4-bit I2C and SMBus low power I/O port
Fabricantes	NXP Semiconductors
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No Preview Available ! www.DataSheet4U.com INTEGRATED CIRCUITS PCA9537 4-bit I2C and SMBus low power I/O port with interrupt and reset Product data sheet Supersedes data of 2004 Sep 30 2004 Nov 29 Philips Semiconductors 1 page Philips Semiconductors 4-bit I2C and SMBus low power I/O port with interrupt and reset SIMPLIFIED SCHEMATIC OF I/O0 TO I/O3 DATA FROM SHIFT REGISTER DATA FROM SHIFT REGISTER WRITE CONFIGURATION PULSE WRITE PULSE CONFIGURATION REGISTER DQ FF CK Q DQ FF CK Q OUTPUT PORT REGISTER READ PULSE Q1 INPUT PORT REGISTER DQ FF CK Q Q2 DATA FROM SHIFT REGISTER WRITE POLARITY PULSE DQ FF CK Q POLARITY INVERSION REGISTER NOTE: At Power-on Reset, all registers return to default values. Figure 3. Simplified schematic of I/O0 to I/O3 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the output port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS. Product data sheet PCA9537 OUTPUT PORT REGISTER DATA VDD ESD PROTECTION DIODE I/O0 TO I/O3 ESD PROTECTION DIODE VSS INPUT PORT REGISTER DATA TO INT POLARITY REGISTER DATA SW02325 2004 Nov 29 5 5 Page Philips Semiconductors 4-bit I2C and SMBus low power I/O port with interrupt and reset Product data sheet PCA9537 AC SPECIFICATIONS SYMBOL PARAMETER STANDARD MODE I2C-bus MIN MAX fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tF tR tSP Operating frequency Bus free time between STOP and START conditions Hold time after (repeated) START condition Repeated START condition setup time Setup time for STOP condition Data in hold time Valid time for ACK condition2 Data out valid time3 Data setup time Clock LOW period Clock HIGH period Clock/Data fall time Clock/Data rise time Pulse width of spikes that must be suppressed by the input filters 0 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 — — — 100 — — — — — 3.45 — — — — 300 1000 50 Port Timing tPV Output data valid tPS Input data setup time tPH Input data hold time Interrupt Timing — 200 100 — 1— tIV tIR RESET Interrupt valid Interrupt reset —4 —4 tW tREC tRESET Reset pulse width Reset recovery time Time to reset 4— 0— 400 — NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. FAST MODE I2C-bus MIN MAX 0 400 1.3 — 0.6 — 0.6 — 0.6 — 0— 0.1 0.9 50 — 100 — 1.3 — 0.6 20 + 0.1 Cb1 20 + 0.1 Cb1 — — 300 300 50 — 200 100 — 1— —4 —4 4— 0— 400 — UNITS kHz µs µs µs µs ns µs ns ns µs µs ns ns ns ns ns µs µs µs ns ns ns SDA tBUF tLOW tR tF SCL P tHD;STA S tHD;DAT tHIGH tSU;DAT tHD;STA tSU;STA Sr Figure 12. Definition of timing tSP tSU;STO P SU00645 2004 Nov 29 11 11 Page

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