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Número de pieza | 56F8165 | |
Descripción | (56F8365 / 56F8165) 16-bit Digital Signal Controllers | |
Fabricantes | Freescale Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de 56F8165 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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56F8365/56F8165
Data Sheet
Preliminary Technical Data
56F8300
16-bit Digital Signal Controllers
MC56F8365
Rev. 6.0
06/2006
freescale.com
1 page 56F8365/56F8165 Features
Part 1 Overview
1.1 56F8365/56F8165 Features
1.1.1 Core
• Efficient 16-bit 56800E family controller engine with dual Harvard architecture
• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• Arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/EOnCE debug programming interface
1.1.2 Differences Between Devices
Table 1-1 outlines the key differences between the 56F8365 and 56F8165 devices.
Table 1-1 Device Differences
Feature
56F8365
Guaranteed Speed
Program RAM
Data Flash
PWM
CAN
Quad Timer
Quadrature Decoder
Temperature Sensor
60MHz/60 MIPS
4KB
32KB
2x6
2
4
2x4
1
56F8165
40MHz/40MIPS
Not Available
Not Available
1x6
Not Available
2
1x4
Not Available
Freescale Semiconductor
Preliminary
56F8365 Technical Data, Rev. 6.0
5
5 Page Architecture Block Diagram
5
JTAG / EOnCE
CHIP
TAP
Controller
pdb_m[15:0]
pab[20:0]
cdbw[31:0]
56800E
Boot
Flash
Program
Flash
Program
RAM
EMI*
11 Address
4 Data
6 Control
TAP
Linking
Module
xab1[23:0]
xab2[23:0]
Data RAM
External
JTAG
Port
cdbr_m[31:0]
xdb2_m[15:0]
Data
Flash
IPBus
Bridge
To Flash
Control Logic
NOT available on the 56F8165 device.
* EMI not functional in this package; since only part of
the address/data bus is bonded out, use as GPIO pins
IPBus
Figure 1-1 System Bus Interfaces
Flash
Memory
Module
Note:
Note:
Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
Freescale Semiconductor
Preliminary
56F8365 Technical Data, Rev. 6.0
11
11 Page |
Páginas | Total 70 Páginas | |
PDF Descargar | [ Datasheet 56F8165.PDF ] |
Número de pieza | Descripción | Fabricantes |
56F8165 | (56F8365 / 56F8165) 16-bit Digital Signal Controllers | Freescale Semiconductor |
56F8166 | (56F8166 / 56F8366) 16-bit Digital Signal Controllers | Freescale Semiconductor |
56F8167 | (56F8167 / 56F8367) 16-bit Digital Signal Controllers | Freescale Semiconductor |
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