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PDF ADP3193 Data sheet ( Hoja de datos )
| Número de pieza | ADP3193 | |
| Descripción | 8-Bit Programmable Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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8-Bit Programmable 2- to 3-Phase
Synchronous Buck Controller
ADP3193
FEATURES
Selectable 2- or 3-phase operation at up to 1 MHz per phase
±7.7 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external high
power drivers
Enhanced PWM flex mode for excellent load transient
performance
Active current balancing between all output phases
Built-in power-good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable 0.5 V to 1.6 V output supports both
VR10.x and VR11 specifications
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for
Next generation Intel® processors
VRM modules
GENERAL DESCRIPTION
The ADP31931 is a highly efficient, multiphase, synchronous buck
switching regulator controller optimized for converting a 12 V
main supply into the core supply voltage required by high per-
formance Intel processors. It uses an internal 8-bit DAC to read
a voltage identification (VID) code directly from the processor,
which is used to set the output voltage between 0.5 V and 1.6 V.
This device uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase relation-
ship of the output signals can be programmed to provide 2- or
3-phase operation, allowing for the construction of up to three
complementary buck switching stages.
The ADP3193 also includes programmable no load offset and
slope functions to adjust the output voltage as a function of the
load current, optimally positioning it for a system transient. The
ADP3193 also provides accurate and reliable short-circuit
protection, adjustable current limiting, and a delayed power-
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
FUNCTIONAL BLOCK DIAGRAM
GND 14
VCC
23
SHUNT
REGULATOR
UVLO
SHUTDOWN
850mV –
EN 1
+
DAC
+ 150mV
CSREF
–
+
+
DAC –
– 350mV
PWRGD 2
DELAY
ILIMIT 8
DELAY 7
RT RAMPADJ
9 10
OSCILLATOR
+
CMP
–
SET EN
RESET
15 OD
22 PWM1
+
CMP
–
+
CMP
–
21 PWM2
RESET
2/3-PHASE
DRIVER LOGIC
20 PWM3
RESET
CROWBAR
CURRENT
LIMIT
19 SW1
18 SW2
17 SW3
13 CSCOMP
CURRENT
MEASUREMENT
+
11 CSREF
AND LIMIT
– 12 CSSUM
IREF 16
COMP 5
4 FB
FBRTN 3
PRECISION
REFERENCE
VIDSEL 32
VC DAC
24 25 26 27 28 29 30 31
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
BOOT
VOLTAGE
AND
SOFT START
CONTROL
6 SS
ADP3193
Figure 1.
The ADP3193 has a built-in shunt regulator that allows the part
to be connected to the 12 V system supply through a series resistor.
The ADP3193 is specified over the extended commercial
temperature range of 0°C to 85°C and is available in a
32-lead LFCSP.
1 Protected by U.S. Patent Number 6,683,441; other patents pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
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TEST CIRCUITS
8-BIT CODE
32
1.25V
1kΩ
10nF
10nF
1 EN
PWRGD
FBRTN
FB
COMP
SS
DELAY
ILIMIT
ADP3193
VID7
VCC
PWM1
PWM2
PWM3
SW1
SW2
SW3
250kΩ
100kΩ
12V
680Ω
680Ω
+ 1µF
100nF
20kΩ
100nF
Figure 2. Closed-Loop Output Voltage Accuracy
12V
680Ω
680Ω
ADP3193
VCC
23
39kΩ
1kΩ
1V
CSCOMP
13
100nF
CSSUM
12
CSREF
11
GND
14
VOS =
CSCOMP – 1V
40
Figure 3. Current Sense Amplifier VOS
ADP3193
12V ADP3193
680Ω
10kΩ
680Ω
VCC
23
COMP
5
FB
4
CSREF
11 +
1V
GND
14
VID
DAC
Figure 4. Positioning Voltage
Rev. A | Page 5 of 32
5 Page 
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ADP3193
with respect to the VID DAC. The main loop compensation is
incorporated into the feedback network between FB and COMP.
CURRENT REFERENCE
The IREF pin is used to set an internal current reference. This
reference current sets IFB, IDELAY, ISS, and ILIMIT. A resistor to
ground programs the current based on the 1.5 V output.
1.5 V
IREF =
R IREF
Typically, RIREF is set to 100 kΩ to program IREF = 15 μA. The
following currents are then equal to
IFB = IREF = 15 μA
IDELAY = IREF = 15 μA
ISS = IREF = 15 μA
ILIMIT = 2/3 (IREF) = 10 μA
ENHANCED PWM MODE
Enhanced PWM mode is intended to improve the transient
response of the ADP3193 to a load step up. In previous
generations of controllers, when a load step up occurred, the
controller had to wait until the next turn-on of the PWM signal
to respond to the load change. Enhanced PWM mode allows
the controller to immediately respond when a load step up
occurs. This allows the phases to respond more quickly when a
load increase takes place.
DELAY TIMER
The delay times for the start-up timing sequence are set with
a capacitor from the DELAY pin to ground. In UVLO, or when
EN is logic low, the DELAY pin is held at ground. After the
UVLO and EN signals are asserted, the first delay time (TD1 in
Figure 7) is initiated. A current flows out of the DELAY pin to
charge CDLY. This current is equal to IREF, which is normally
15 μA. A comparator monitors the DELAY voltage with a
threshold of 1.7 V. The delay time is therefore set by the IREF
current charging a capacitor from 0 V to 1.7 V. This DELAY pin
is used for multiple delay timings (TD1, TD3, and TD5) during
the start-up sequence. In addition, DELAY is used for timing
the current-limit latch off, as explained in the Current-Limit,
Short-Circuit, and Latch-Off Protection section.
SOFT START
The soft start times for the output voltage are set with a
capacitor from the SS pin to ground. After TD1 and the phase
detection cycle have been completed, the SS time (TD2 in
Figure 7) starts. The SS pin is disconnected from GND, and
the capacitor is charged up to the 1.1 V boot voltage by the
SS amplifier, which has an output current equal to IREF
(normally 15 μA). The voltage at the FB pin follows the ramping
voltage on the SS pin, limiting the inrush current during
startup. The soft start time depends on the value of the boot
voltage and CSS.
Once the SS voltage is within 100 mV of the boot voltage, the
boot voltage delay time (TD3 in Figure 7) is started. The end of
the boot voltage delay time signals the beginning of the second
soft start time (TD4 in Figure 7). The SS voltage now changes
from the boot voltage to the programmed VID DAC voltage
(either higher or lower) using the SS amplifier with the output
current equal to IREF. The voltage of the FB pin follows the
ramping voltage of the SS pin, limiting the inrush current
during the transition from the boot voltage to the final DAC
voltage. The second soft start time depends on the boot voltage,
the programmed VID DAC voltage, and CSS.
If EN is taken low or if VCC drops below UVLO, DELAY, and
SS are reset to ground to be ready for another soft start cycle.
Figure 8 shows typical start-up waveforms for the ADP3193.
1
2
3
4
CH1 1V
CH3 1V
CH2 1V
CH4 10V
M 1ms
T 40.4%
A CH1 700mV
Figure 8. Typical Start-Up Waveforms
(Channel 1: CSREF, Channel 2: DELAY,
Channel 3: SS, Channel 4: Phase 1 Switch Node)
CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCH-
OFF PROTECTION
The ADP3193 compares a programmable current-limit set
point to the voltage from the output of the current-sense
amplifier. The level of current limit is set with the resistor
from the ILIMIT pin to ground. During operation, the current
from ILIMIT is equal to 2/3 of IREF, giving 10 μA normally.
This current through the external resistor sets the ILIMIT
voltage, which is internally scaled to give a current limit
threshold of 82.6 mV/V. If the difference in voltage between
CSREF and CSCOMP rises above the current-limit threshold,
the internal current-limit amplifier controls the internal COMP
voltage to maintain the average output current at the limit.
If the limit is reached and TD5 in Figure 7 has completed, a
latch-off delay time starts, and the controller shuts down if the
fault is not removed. The current-limit delay time shares the
DELAY pin timing capacitor with the start-up sequence timing.
However, during current limit, the DELAY pin current is
Rev. A | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP3193.PDF ] | |
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