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WED2CG472512V-D2 데이터시트 PDF




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부품번호 WED2CG472512V-D2 기능
기능 DUAL KEY DIMM SRAM MODULE
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WED2CG472512V-D2 데이터시트, 핀배열, 회로
www.DataSheet4U.com
White Electronic Designs
WED2CG472512V-D2
ADVANCED*
16MB (4x512Kx72) SYNC / SYNC BURST,
DUAL KEY DIMM SRAM MODULE
FEATURES
DESCRIPTION
4x512Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Linear and Sequential Burst Support via MODE pin
Clock Controlled Registered Module Enable (EM#)
Clock Controlled Registered Bank Enables (E1#, E2#,
E3#, E4#)
Clock Controlled Byte Write Mode Enable (BWE#)
Clock Controlled Byte Write Enables (BW1# - BW8#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
Asynchronous Output Enable (G#)
Internally Self-Timed Write
Individual Bank Sleep Mode Enables (ZZ1, ZZ2, ZZ3, ZZ4)
Gold Lead Finish
3.3V ± 10% Operation
Frequency(s): 100, 83, 67, 50MHz
Access Speed(s): tKHQV = 7.5, 9, 10, 12, 15ns
Common Data I/O
High Capacitance (30pF) Drive, at Rated Access Speed
Single Total Array Clock
The WED2CG472512V is a Synchronous/Synchronous
Burst SRAM, 84 position Dual Key; Double High DIMM
(168 contacts) Module, organized as 4x512Kx72. The
Module contains sixteen (16) Synchronous Burst RAM
devices, packaged in the industry standard JEDEC
14mmx20mm TQFP placed on a Multilayer FR4 Substrate.
The Module Architecture is defined as a Sync/SyncBurst,
Flow-Through, with support for either linear or sequential
burst. This Module provides high performance, 2-1-1-1
accesses when used in Burst Mode, and when used in
Synchronous Only Mode, provides a high performance
cost advantage over BiCMOS asynchronous device
architectures.
Synchronous Only operations are performed via strapping
ADSC# Low, and ADSP#/ADV# High, which provides for
Ultra Fast Accesses in Read Mode while providing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in
relation to an externally supplied clock, Registered
Address, Registered Global Write, Registered Enables as
well as an Asynchronous Output Enable. This Module has
been defined with full flexibility, which allows individual
control of each of the eight bytes, as well as Quad Words
in both Read and Write Operations.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Aug. 2002
Rev. B
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




WED2CG472512V-D2 pdf, 반도체, 판매, 대치품
White Electronic Designs WED2CG472512V-D2
ADVANCED
SYNC BURST – TRUTH TABLE
Operation
E1# E2# E3# E4# ADSP# ADSC# ADV# GW# G# CK
DQ Addr. Used
Deselected Cycle, Power Down; Bank 1 H X * * X L X X X L-H High-Z None
Deselected Cycle, Power Down; Bank 2 X H * * X L X X X L-H High-Z None
Read Cycle, Begin Burst; Bank 1
L H * * L X X X L L-H Q External
Read Cycle, Begin Burst; Bank 1
L H * * L X X X H L-H High-Z External
Read Cycle, Begin Burst, Bank 2
H L * * L X X X L L-H Q External
Read Cycle, Begin Burst; Bank 2
H L * * L X X X H L-H High-Z External
Write Cycle, Begin Burst; Bank 1
L H * * H L X L X L-H D External
Write Cycle, Begin Burst; Bank 2
H L * * H L X L X L-H D External
Read Cycle, Begin Burst; Bank 1
L H * * H L X H L L-H Q External
Read Cycle, Begin Burst; Bank 1
L H * * H L X H H L-H High-Z External
Read Cycle, Begin Burst; Bank 2
H L * * H L X H L L-H Q External
Read Cycle, Begin Burst; Bank 2
H L * * H L X H H L-H High-Z External
Read Cycle, Continue Burst; Bank 1 X H * * X H L
H L L-H Q
Next
Read Cycle, Continue Burst; Bank 1
X H **
XH
L
H H L-H High-Z Next
Read Cycle, Continue Burst; Bank 2 H X * * X H L
H L L-H Q
Next
Read Cycle, Continue Burst; Bank 2
H X **
XH
L
H H L-H High-Z Next
Read Cycle, Continue Burst; Bank 1 H H * * X H L
H L L-H Q
Next
Read Cycle, Continue Burst; Bank 1
H H **
XH
L
H H L-H High-Z Next
Read Cycle, Continue Burst; Bank 2 H H * * X H L
H L L-H Q
Next
Read Cycle, Continue Burst; Bank 2
H H **
XH
L
H H L-H High-Z Next
Write Cycle, Continue Burst; Bank 1 X H * * H H L
L X L-H D
Next
Write Cycle, Continue Burst; Bank 1 H H * * X H L
L X L-H D
Next
Write Cycle, Continue Burst; Bank 2 H X * * H H L
L X L-H D
Next
Write Cycle, Continue Burst; Bank 2 H H * * X H L
L X L-H D
Next
Read Cycle, Suspend Burst; Bank 1
X H **
HHH
H L L-H Q Current
Read Cycle, Suspend Burst; Bank 1
X H **
HHH
H H L-H High-Z Current
Read Cycle, Suspend Burst; Bank 2
H X **
HHH
H L L-H Q Current
Read Cycle, Suspend Burst; Bank 2
H X **
HHH
H H L-H High-Z Current
Read Cycle, Suspend Burst; Bank 1 H H * * X H H H L L-H Q Current
Read Cycle, Suspend Burst; Bank 1 H H * * X H H H H L-H High-Z Current
Read Cycle, Suspend Burst; Bank 2 H H * * X H H H L L-H Q Current
Read Cycle, Suspend Burst; Bank 2 H H * * X H H H H L-H High-Z Current
Write Cycle, Suspend Burst; Bank 1
X H **
HHH
L X L-H D Current
Write Cycle, Suspend Burst; Bank 1
H H **
XHH
L X L-H D Current
Write Cycle, Suspend Burst; Bank 2
H X **
HHH
L X L-H D Current
Write Cycle, Suspend Burst; Bank 2
H H **
XHH
L X L-H D Current
Note A: All truth Table Functions Repeat for Bank 3 (E3#) and Bank 4 (E4#).
Operation
Synchronous Write - Bank 1
Synchronous Read - Bank 1
Synchronous Write - Bank 2
Synchronous Read - Bank 2
Synchronous Write - Bank 3
Synchronous Read - Bank 3
Synchronous Write - Bank 4
Synchronous Read - Bank 4
Snooze Mode
SYNCHRONOUS ONLY – TRUTH TABLE
E1# E2# E3# E4# GW# G#
L HHH L H
L HHHH L
H L HH L H
H L HHH L
HH L H L H
HH L HH L
HHHL LH
HHH L H L
XXXXXX
ZZ
L
L
L
L
L
L
L
L
H
CK DQ
High-Z
High-Z
High-Z
High-Z
X High-Z
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Aug. 2002
Rev. B
4 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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WED2CG472512V-D2 전자부품, 판매, 대치품
White Electronic Designs WED2CG472512V-D2
ADVANCED
FIG. 3
CK
Ex#
ADDR
G#
GW#
DQ0-63
SYNCHRONOUS ONLY READ CYCLE
tKHKH
tKHKL tKLKH
Addr 1
tKHQV
tKHQX
Q(Addr 1)
Read Cycle
tKHQZ
tAVKH
Addr 1
Addr 2
tKHAX
tGLQV
tGLQX
Q(Addr 1)
Q(Addr 2)
Back to Back Read
tKHQX1
FIG. 4
CK
ADSP#
ADSC#
ADDR
BWx#,
GW#
CE#
ADV#
G#
DQ
SYNC-BURST READ CYCLE
tKHKH
tKHKL tKLKH
tSPVKH
tKHSPX
tAVKH
tKHAX
tSCVKH
tKHSCX
tEVKH
tKHEX
tGLQV
tGLQX
tKHQX
Read Cycle
tGHQX
tGHQZ
tAVVKH
tKHAVX
tKHQV
tKHQX
Burst Read Cycle
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Aug. 2002
Rev. B
7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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DUAL KEY DIMM SRAM MODULE

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