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부품번호 WED2DL32512V 기능
기능 512Kx32 Synchronous Pipeline Burst SRAM
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WED2DL32512V 데이터시트, 핀배열, 회로
www.DataSheet4U.com
WED2DL32512V
512Kx32 Synchronous Pipeline Burst SRAM PRELIMINARY*
FEATURES
s Fast clock speed: 200, 166, 150 & 133MHz
s Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
s Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
s Single +3.3V power supply (VDD)
s Separate +3.3V or +2.5V isolated output buffer supply (VDDQ)
s Snooze Mode for reduced-power standby
s Single-cycle deselect
s Common data inputs and data outputs
s Individual Byte Write control and Global Write
s Clock-controlled and registered addresses, data I/Os and control signals
s Burst control (interleaved or linear burst)
s Packaging:
• 119-bump BGA package
s Low capacitive bus loading
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed, low-
power CMOS designs that are fabricated using an advanced CMOS
process. WEDC’s 16Mb SyncBurst SRAMs integrate two 512K x 16
SRAMs into a single BGA package to provide 512K x 32 configura-
tion. All synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The synchronous
inputs include all addresses, all data inputs, active LOW chip enable
(CE), burst control input (ADSC) and byte write enables (BW0-3).
Asynchronous inputs include the output enable (OE), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE)
that selects between interleaved and linear burst modes. Write cycles
can be from one to four bytes wide, as controlled by the write control
inputs. Burst operation can be initiated with the address status
controller (ADSC) input.
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
FIG. 1
PIN CONFIGURATION
(TOP VIEW)
123 4 5
A VDDQ SA
SA
NC
SA
B NC SA SA ADSC SA
C NC SA SA VDD SA
D DQc NC VSS NC VSS
E DQc DQc VSS CE VSS
F VDDQ DQc VSS OE VSS
G DQc DQc BWc NC BWb
H DQc DQc VSS NC VSS
J VDDQ VDD NC
VDD
NC
K DQd DQd VSS
CLK
VSS
L DQd DQd BWd NC BWa
M VDDQ DQd VSS BWE VSS
N DQd DQd VSS
SA1
VSS
P DQd NC VSS SA0 VSS
R NC SA MODE VDD NC
T NC NC SA SA SA
U VDDQ DC
DC
DC
DC
NOTE: DC = Do Not Connect
6
SA
SA
SA
NC
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
NC
SA
NC
NC
7
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
ZZ
VDDQ
SA
CLK
ADSC
OE
BWE
CE
MODE
ZZ
BWa
BWb
BLOCK DIAGRAM
512K x 16
SSRAM
DQa
DQb
512K x 16
SSRAM
DQc
DQd
BWc
BWd
January 2000 Rev. 0
1 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com




WED2DL32512V pdf, 반도체, 판매, 대치품
WED2DL32512V
PARTIAL TRUTH TABLE - WRITE COMMANDS
Function
BWE BWa BWb BWc
BWd
Read
HXXX
X
Read
LHHH
H
Write Byte “a”
L LHH
H
Write All Bytes
LLLL
L
NOTE: Using BWE and BWa through BWd, any one or more bytes may be written.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply relative to VSS
Voltage on VDDQ Supply relative to VSS
VIN (DQx)
VIN (Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
-0.5V to +4.6V
-0.5V to +4.6V
-0.5V to VDDQ +0.5V
-0.5V to VDD +0.5V
-55°C to +125°C
100 mA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS
Description
Symbol
Input High (Logic 1)Voltage
VIH
Input Low (Logic 0) Voltage
VIL
Input Leakage Current
ILI
Ouptut Leakage Current
ILO
Output High Voltage
VOH
Output Low Voltage
VOL
Supply Voltage
VDD
Isolated Output Buffer SupplyVDDQ
NOTES:
1. All voltages referenced to Vss (GND).
2. MODE has an internal pull-up, and input leakage = ±10µA.
Conditions
0V VIN VDD
Output(s) disabled, 0V VIN VDD
IOH = -4.0mA
IOL = 8.0mA
3.134
Min Max
Units Notes
2.0
-0.3
-1.0
-1.0
2.4
3.135
3.6
VDD +0.3
0.8
1.0
1.0
0.4
3.6
V
V
V
mA
mA
V
V
V
1
1
2
1
1
1
DC CHARACTERISTICS
Description
Symbol
Conditions
Typ
200* 166 150
MHz MHz MHz
133
MHz
Power Supply
Current: Operating
IDD
Device selected; All inputs VIL or 3 VIH; Cycle time 3 tKC MIN;
VDD = MAX; Outputs open
CMOS Standby
ISB2
Device deselected; VDD = MAX; All inputs VSS + 0.2
or VDD - 0.2; All inputs static; CLK frequency = 0
TTL Standby
ISB3
Device deselected; VDD = MAX; All inputs VIL or VIH;
All inputs static; CLD frequency = 0
Clock Running
ISB4
Device deselected; VDD = MAX; All inputs VSS + 0.2
or VDD -0.2; Cycle time 3 tKC MIN
950 800 740 600
10 20 20 20
20
20 40 40 40
40
80 220 180 160 140
* Advanced Information
NOTES:
1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading.
2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device is active (not in power-down mode).
3. Typical values are measured at 3.3V, 25°C and 133MHz.
Units
mA
mA
mA
mA
Notes
1,2,3
2,3
2,3
2,3
Description
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
NOTES:
1. This parameter is sampled.
BGA CAPACITANCE
Conditions
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
Symbol
CI
CO
CA
CCK
Typ
3
4
3
2.5
Max
6
5
5
4
Units
pF
pF
pF
pF
Notes
1
1
1
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
4

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WED2DL32512V 전자부품, 판매, 대치품
WED2DL32512V
FIG. 3 READ TIMING DIAGRAM
t KH K H
tKHKL tKLKH
CLK
ADSC
CE
ADDR
OE
WRITE
tSC VKH
tEVKH
tAVKH
A1 A2 A3 A4
tKHAX
tOE LQ V
tOE LQ X
tKHSC X
tKHEX
A5
t OE H QZ
DQ
tKH Q X
tKH Q Z
tKH Q V
Q(A1)
Q(A2) Q(A2+1) Q(A2+2) Q(A2+3)
NOTES:
1. Q (A2) refers to output from address A2. Q (A2+1) refers to output from the next internal burst address following A2.
DON’T CARE
UNDEFINED
7 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

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WED2DL32512V

512Kx32 Synchronous Pipeline Burst SRAM

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