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WED2ZL361MV 데이터시트 PDF




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부품번호 WED2ZL361MV 기능
기능 Synchronous Pipeline Burst NBL SRAM
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WED2ZL361MV 데이터시트, 핀배열, 회로
www.DataSheet4U.com
White Electronic Designs
WED2ZL361MV
1Mx36 Synchronous Pipeline Burst NBL SRAM
FEATURES
Fast clock speed: 166, 150, 133, and 100MHz
Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and
5.0ns
Single +3.3V ± 5% power supply (VCC)
Snooze Mode for reduced-standby power
Individual Byte Write control
Clock-controlled and registered addresses, data
I/Os and control signals
Burst control (interleaved or linear burst)
Packaging:
• 119-bump BGA package
Low capacitive bus loading
This product is subject to change without notice.
DESCRIPTION
The WEDC SyncBurst — SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDC’s 32Mb
SyncBurst SRAMs integrate two 1M x 18 SRAMs into a
single BGA package to provide 1M x 36 configuration. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single-clock input (CLK). The
NBL or No Bus Latency Memory utilizes all the bandwidth
in any combination of operating cycles. Address, data
inputs, and all control signals except output enable and
linear burst order are synchronized to input clock. Burst
order control must be tied “High or Low.” Asynchronous
inputs include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are
internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip write
pulse generation and provides increased timing flexibility
for incoming signals.
FIGURE 1 – PIN CONFIGURATION
(Top View)
Block Diagram
1234567
A VCC SA SA SA SA SA VCC
B SA CE2 SA ADV# SA CE2# NC
C NC SA SA VCC SA SA NC
D DQC DQPC VSS NC VSS DQPB DQB
E DQC DQC VSS CE1# VSS DQB DQB
F VCC DQC VSS OE# VSS DQB VCC
G DQC DQC BWC# SA BWB# DQB DQB
H DQC DQC VSS WE# VSS DQB DQB
J VCC VCC NC VCC NC VCC VCC
K DQD DQD VSS CLK VSS DQA DQA
L DQD DQD BWD# NC BWA# DQA DQA
M VCC DQD VSS CKE# VSS DQA VCC
N DQD DQD VSS SA1 VSS DQA DQA
P DQD DQPD VSS SA0 VSS DQPA DQA
R NC SA LBO VCC NC SA NC
T NC NC SA SA SA NC ZZ
U VCC NC NC NC NC NC VCC
CLK
CKE#
ADV#
LBO#
CE1#
CE2
CE2#
OE#
WE#
ZZ
1M x 18
CLK
CKE#
ADV#
LBO#
CS1#
CS2
CS2#
OE#
WE#
ZZ
1M x 18
CLK
CKE#
ADV#
LBO#
CS1#
CS2
CS2#
OE#
WE#
ZZ
Address Bus
(SA0 - SA19)
DQc, DQd
DQPc, DQPd
DQa, DQb
DQPa, DQPb
DQa - DQd
DQPa - DQPd
June 2004
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




WED2ZL361MV pdf, 반도체, 판매, 대치품
White Electronic Designs
WED2ZL361MV
Absolute Maximum Ratings*
Voltage on VCC Supply Relative to VSS
VIN (DQx)
VIN (Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
-0.3V to +4.6V
-0.3V to +4.6V
-0.3V to +4.6V
-65°C to +150°C
100mA
* Stress greater than those listed under “Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended
periods may affect reliability.
Recommended DC Operating Conditions Voltage Referenced to:
VSS = 0V, = 0°C ≤ TA ≤ +70°C; Commercial or -40°C ≤ TA ≤ +85°C; Industrial
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Symbol
VIH
VIL
ILI
ILO
VOH
VOL
VCC
Conditions
0V ≤ VIN ≤ VCC
Output(s) Disabled, 0V ≤ VIN ≤ VCC
IOH = -4.0mA
IOL = 8.0mA
Min
2.0
-0.3
-5
-5
2.4
3.135
Max
VCC +0.5
0.8
5
5
0.4
3.465
NOTES:
1. All voltages referenced to VSS (GND)
2. ZZ pin has an internal pull-up, and input leakage = ± 10µA.
Units
V
V
µA
µA
V
V
V
Notes
1
1
2
1
1
1
DC Characteristics
166 150 133 100
Description
Symbol Conditions
Typ MHz MHz MHz MHz Units Notes
Power Supply
Current: Operating
Power Supply
Current: Standby
Power Supply
Current: Current
Clock Running
Standby Current
IDD Device Selected; All Inputs ≤ VIL or VIH; Cycle Time =
TCYC MIN; VCC = MAX; Output Open
840 800 760 640 mA 1, 2
ISB2 Device Deselected; VCC = MAX; All Inputs ≤ VSS + 0.2 or 30 60 60 60 60 mA 2
VCC - 0.2; All Inputs Static; CLK Frequency = 0; ZZ ≤ VIL
ISB3 Device Selected; All Inputs ≤ VIL or VIH; Cycle Time =
TCYC MIN; VCC = MAX; Output Open; ZZ VCC - 0.2V
30 60 60
60 60 mA
2
ISB4 Device Deselected; VCC = MAX; All Inputs ≤ VSS + 0.2 or
VCC - 0.2; Cycle Time = TCYC MIN; ZZ ≤ VIL
240 220 180 160 mA 2
NOTES:
1. IDD is specified with no output current and increases with faster cycle times.
IDD increases with faster cycle times and greater output loading.
2. Typical values are measured at 3.3V, 25°C, and 10ns cycle time.
Description
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
NOTES: 1. This parameter is sampled.
June 2004
Rev. 3
BGA Capacitance
Symbol
CI
CO
CA
CCK
Conditions
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
Typ Max Units Notes
5 7 pF 1
6 8 pF 1
5 7 pF 1
3 5 pF 1
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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WED2ZL361MV 전자부품, 판매, 대치품
White Electronic Designs
WED2ZL361MV
FIGURE 3 – TIMING WAVEFORM OF READ CYCLE
Clock
Address
tAS tAH
A1
WRITE#
tWS tWH
CEx#
ADV
tCSS tCSH
tADVS
tADVH
A2
tCH tCL
A3
OE#
Data Out
tOE
tLZOE
tHZOE
tCD
tOH
tHZC
Q1-1 Q2-1 Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4
NOTES: WRITE = L means WE = L, and BWx = L
CEx# refers to the combination of CE1#, CE2 and CE2#.
Don't Care
Undefined
June 2004
Rev. 3
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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