PDF WED2ZL64512S Data sheet ( Hoja de datos )

Número de pieza	WED2ZL64512S
Descripción	Synchronous Pipeline NBL SRAM
Fabricantes	White Electronic
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No Preview Available ! www.DataSheet4U.com White Electronic Designs WED2ZL64512S 512K x 64 Synchronous Pipeline NBL SRAM FEATURES  Fast clock speed: 166, 150, 133, and 100MHz  Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns  Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns  Seperate +2.5V ± 5% power supplys for core I/O (VCC + VCCQ)  Double Word Write Control  Clock-controlled and registered addresses, data I/Os and control signals  Packaging: • 119 bump BGA package  Low capacitive bus loading DESCRIPTION The WEDC SyncBurst - SRAM family employs high- speed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 32Mb Sync SRAM integrate two 512K x 32 SRAMs into a single BGA package to provide 512K x 64 conﬁguration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CK). The NBL or No Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable are synchronized to input clock. Output Enable controls the outputs at any given time and to Asynchronous Input. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing ﬂexibility for incoming signals. NOTE: NBL = No Bus Latency is equivalent to the industry ZBT™ devices. FIG. 1 PIN CONFIGURATION (TOP VIEW) 123456789 A DQF DQF DQF DQF NC DQG DQG DQG DQG B DQF DQF DQF DQF NC DQG DQG DQG DQG C DQE DQE DQE DQE NC DQH DQH DQH DQH D DQE DQE DQE DQE NC DQH DQH DQH DQH E NC NC NC VCCQ VCCQ VCCQ NC NC NC F SA VCCQ VCC VCC VCC VCC VCC VCCQ SA G SA CE# VSS VSS VSS VSS VSS SA SA H SA NC VSS WE1# VSS VSS VSS SA SA J SA18 CE2# SSCK OE# NC NC NC SA1 SA0 K SA CE2 VSS WE0# VSS VSS VSS SA SA L SA NC VSS VSS VSS VSS VSS SA SA M SA VCCQ VCC VCC VCC VCC VCC VCCQ SA N NC NC NC VCCQ VCCQ VCCQ NC NC NC P DQD DQD DQD DQD NC DQA DQA DQA DQA R DQD DQD DQD DQD NC DQA DQA DQA DQA T DQC DQC DQC DQC NC DQB DQB DQB DQB U DQC DQC DQC DQC NC DQB DQB DQB DQB OEB WEB_LW CK CS2B CS2 CS1B BLOCK DIAGRAM SA 0 – 18 DQ 0 – 31 DQ 32 – 63 A0 – A18 OE# WE# CK CS2# CS2 CS1# U1 DQ 0 – 31 512K x 36 WEB_HW A0 – A18 OE# WE# CK CS2# CS2 CS1# U2 DQ 0 – 31 512K x 36 White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. October 2001 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs FIG. 3 TIMING WAVEFORM OF READ CYCLE Clock Address WE0B WE1B CEx# tAS tAH A1 tWS tWH tCSS tCSH A2 tCH tCL OEB# Data Out tOE tLZOE tHZOE Q1-1 tCD tOH Q2-1 NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2, CE2#. Don't Care Undefined WED2ZL64512S White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. October 2001 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page

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