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PDF A43L1632 Data sheet ( Hoja de datos )
| Número de pieza | A43L1632 | |
| Descripción | 512K X 32 Bit X 4 Banks Synchronous DRAM | |
| Fabricantes | AMIC Technology | |
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A43L1632
Preliminary
512K X 32 Bit X 4 Banks Synchronous DRAM
Document Title
512K X 32 Bit X 4 Banks Synchronous DRAM
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
December 28, 2004
Remark
Preliminary
PRELIMINARY (December, 2004, Version 0.0)
AMIC Technology, Corp.
1 page  
A43L1632
Pin Descriptions
Symbol
CLK
CS
CKE
A0~A10
BS0, BS1
Name
Description
System Clock
Active on the positive going edge to sample all inputs.
Chip Select
Disables or Enables device operation by masking or enabling all inputs except CLK,
CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
Clock Enable
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA10, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
Bank Select Address
Selects band for read/write during column address latch time.
RAS
Latches row addresses on the positive going edge of the CLK with RAS low.
Row Address Strobe
Enables row access & precharge.
CAS
Column Address
Strobe
WE Write Enable
DQM0-3
Data Input/Output
Mask
DQ0-31
Data Input/Output
VDD/VSS
Power
Supply/Ground
VDDQ/VSSQ
Data Output
Power/Ground
NC/RFU
No Connection
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when DQM0-3 active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +2.5V±0.125V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
PRELIMINARY (December, 2004, Version 0.0)
4
AMIC Technology, Corp.
5 Page 
A43L1632
Simplified Truth Table
Register
Command
Mode Register Set
CKEn-1 CKEn CS RAS CAS WE DQM BS0 A10 A9~A0, Notes
BS1 /AP
H X LL L L X
OP CODE
1,2
Refresh
Auto Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Addr.
H
H L LL L HX
X
LHH H
LH
X
HX X X
X
H X L L H H X V Row Addr.
3
3
3
3
4
Read &
Auto Precharge Disable
Column Addr. Auto Precharge Enable
L Column
4
H X L H L H X V H Addr. 4,5
Write &
Auto Precharge Disable
Column Addr. Auto Precharge Enable
L Column
4
H X L H L L X V H Addr. 4,5
Burst Stop
H X LHH L X
X
Precharge
Bank Selection
Both Banks
VL
H X L L H L X XH X
Clock Suspend or
Active Power Down
Entry
Exit
LHH H
HL
X
HX X X
L H XX X X X
X
Precharge Power Down Mode
Entry
Exit
LHH H
HL
X
HX X X
LVV V
LH
X
HX X X
X
DQM
H
X
VX
6
No Operation Command
LHH H
HX
X
HX X X
X
Deep Power Down Entry
H L LHH L X
X
Deep Power Down Exit
L H XX X X X
X
7
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note : 1. OP Code: Operand Code
A0~A10, BS0, BS1: Program keys. (@MRS)
2. MRS can be issued only when all banks are at precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions is same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only when all banks are at precharge state.
4. BS0, BS1 : Bank select address.
If both BS1 and BS0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.
If both BS1 is “High” and BS0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BS1 and BS0 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BS1 and BS0 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued at every burst length.
6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
7. After Deep Power Down mode exit, a full new initialization of the memory device is mandatory.
PRELIMINARY (December, 2004, Version 0.0)
10
AMIC Technology, Corp.
11 Page | ||
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