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부품번호 | A67P16181 기능 |
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기능 | (A67P06361 / A67P16181) Flow-through ZeBL SRAM | ||
제조업체 | AMIC Technology | ||
로고 | |||
www.DataSheet4U.com
Preliminary
A67P16181/A67P06361 Series
2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM
Document Title
2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM
Revision History
Rev. No.
0.0
0.1
History
Initial issue
Error Correction: delete BWE pin in block diagram
Issue Date
March 25, 2004
August 6, 2004
Remark
Preliminary
PRELIMINARY (August, 2004, Version 0.1)
AMIC Technology, Corp.
Block Diagram (1M X 36)
ZZ
MODE
ADV/LD
MODE
LOGIC
CEN
CLK
CLK
LOGIC
A0-A19
ADDRESS
REGISTERS
ADV/LD
R/W
BW1
BW2
BW3
BW4
WRITE
REGISTRY
&
CONTROL
LOGIC
CE
CE2
CE2
OE
CHIP
ENABLE
LOGIC
A67P16181/A67P06361 Series
BURST
LOGIC
ADDRESS
COUNTER
CLR
WRITE
ADDRESS
REGISTER
9
BYTEa
WRITE
DRIVER
9 BYTEb
WRITE
DRIVER
9 BYTEc
WRITE
DRIVER
9 BYTEd
WRITE
DRIVER
9
9
1MX9X4
MEMORY
9
ARRAY
9
SENSE
AMPS
OUTPUT
BUFFERS
I/O s
FLOW-THROUGH
ENABLE
LOGIC
OUTPUT
ENABLE
LOGIC
DATA-IN
REGISTERS
PRELIMINARY (August, 2004, Version 0.1)
4
AMIC Technology, Corp.
4페이지 A67P16181/A67P06361 Series
Pin Description (continued)
Pin No.
LQFP (X18)
LQFP (X36)
64 64
Symbol
ZZ
88 88 R/ W
74, 73, 72, 69, 68
63, 62, 59, 58
24, 23, 22, 19, 18
13, 12, 9, 8
31
52, 53, 56, 57,
58, 59, 62, 63, 51
68, 69, 72, 73, 74,
75, 78, 79, 80
2, 3, 6, 7, 8, 9, 12,
13,1
18, 19, 22, 23, 24,
25, 28, 29, 30
31
I/Oa
I/Ob
I/Oc
I/Od
MODE
1, 2, 3, 6, 7, 25, 28,
29, 30, 38, 39, 42,
51, 52, 53, 56, 57,
75, 78, 79, 95, 96
38,39,42
15, 16, 41, 65, 91 15, 16, 41, 65, 91
4, 11, 20, 27,
54, 61, 70, 77
4, 11, 20, 27,
54, 61, 70, 77
14, 17, 40, 66, 90 14, 17, 40, 66, 90
5,10,21,26,
55,60,71,76
5,10,21,26,
55,60,71,76
NC
VCC
VCCQ
VSS
VSSQ
Description
Snooze Enable : This active high asynchronous input causes
the device to enter a low-power standby mode in which all
data in the memory array is retained. When active, all other
inputs are ignored.
Read/Write : This active input determines the cycle type
when ADV/LD is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be
converted into WRITEs (and vice versa) other than by
loading a new address. A LOW on this pin permits BYTE
WRITE operations and must meet the setup and hold times
around the rising edge of CLK. Full bus width WRITEs occur
if all byte write enables are LOW.
SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins;
Byte “c” is I/Oc pins; Byte “d” is I/Od pins. Input data must
meet setup and hold times around CLK rising edge.
Mode: This input selects the burst sequence. A LOW on this
pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating.
No Connect : These pins can be left floating or connected to
GND to minimize thermal impedance.
Power Supply
Isolated Output Buffer Supply
Ground : GND.
Isolated Output Buffer Ground
PRELIMINARY (August, 2004, Version 0.1)
7
AMIC Technology, Corp.
7페이지 | |||
구 성 | 총 18 페이지수 | ||
다운로드 | [ A67P16181.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
A67P1618 | (A67P0636 / A67P1618) Pipelined ZeBL SRAM | AMIC Technology |
A67P16181 | (A67P06361 / A67P16181) Flow-through ZeBL SRAM | AMIC Technology |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |