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AT28HC256N PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AT28HC256N
기능 High-speed Parallel EEPROM
제조업체 ATMEL Corporation
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AT28HC256N 데이터시트, 핀배열, 회로
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Features
Fast Read Access Time – 90 ns
Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
Fast Write Cycle Times
– Page Write Cycle Time: 3 ms Maximum
– 1 to 64-byte Page Write Operation
Low Power Dissipation: 300 µA Standby Current (CMOS)
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 105 Cycles
– Data Retention: 10 Years
Single 5V ±10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Description
The AT28HC256N is a high-performance electrically erasable and programmable read
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256N offers
access times to 90 ns with power dissipation of just 440 mW. When the AT28HC256N
is deselected, the standby current is less than 3 mA.
The AT28HC256N is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64
bytes of data are internally latched, freeing the addresses and data bus for other oper-
ations. Following the initiation of a write cycle, the device will automatically write the
latched data using an internal control timer. The end of a write cycle can be detected
by DATA Polling of I/O7. Once the end of a write cycle has been detected a new
access for a read or write can begin.
Atmel’s AT28HC256N has additional features to ensure high quality and manufactura-
bility. The device utilizes internal error correction for extended endurance and
improved data retention characteristics. An optional software data protection mecha-
nism is available to guard against inadvertent writes. The device also includes an extra
64 bytes of EEPROM for device identification or tracking.
Pin Configurations
Pin Name
A0 - A14
CE
OE
WE
I/O0 - I/O7
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
LCC, PLCC
Top View
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
NC 12
I/O0 13
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
256 (32K x 8)
High-speed
Parallel
EEPROM
AT28HC256N
3446B–PEEPR–4/04




AT28HC256N pdf, 반도체, 판매, 대치품
SDP is enabled by the host system issuing a series of three write commands; three spe-
cific bytes of data are written to three specific addresses (refer to “Software Data
Protection” algorithm). After writing the 3-byte command sequence and after tWC the
entire AT28HC256N will be protected against inadvertent write operations. It should be
noted, that once protected the host may still perform a byte or page write to the
AT28HC256N. This is done by preceding the data to be written by the same 3-byte com-
mand sequence.
Once set, SDP will remain active unless the disable command sequence is issued.
Power transitions do not disable SDP and SDP will protect the AT28HC256N during
power-up and power-down conditions. All command sequences must conform to the
page write timing specifications. It should also be noted that the data in the enable and
disable command sequences is not written to the device and the memory addresses
used in the sequence may be written with data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the three byte command
sequence will start the internal write timers. No data will be written to the device; how-
ever, for the duration of tWC, read operations will effectively be polling operations.
DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM memory are available to the
user for device identification. By raising A9 to 12V ± 0.5V and using address locations
7FC0H to 7FFFH the additional bytes may be written to or read from in the same man-
ner as the regular memory array.
OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte soft-
ware code. Please see “Software Chip Erase” application note for details.
4 AT28HC256N
3446B–PEEPR–4/04

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AT28HC256N 전자부품, 판매, 대치품
AC Write Characteristics
Symbol
Parameter
tAS, tOES
Address, OE Setup Time
tAH Address Hold Time
tCS Chip Select Setup Time
tCH Chip Select Hold Time
tWP Write Pulse Width (WE or CE)
tDS Data Setup Time
tDH, tOEH
Data, OE Hold Time
tDV Time to Data Valid
Notes: 1. NR = No Restriction.
AC Write Waveforms
WE Controlled
tOES
tAS
tCS
Min
0
50
0
0
100
50
0
NR(1)
tOEH
tAH tCH
tWP
tDS
tWPH
tDH
CE Controlled
tOES
tAS
tCS
tOEH
tAH tCH
tWP
tDV
tDS
tWPH
tDH
AT28HC256N
Max Units
ns
ns
ns
ns
ns
ns
ns
3446B–PEEPR–4/04
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관련 데이터시트

부품번호상세설명 및 기능제조사
AT28HC256

256K (32K x 8) High-speed Parallel EEPROM

ATMEL Corporation
ATMEL Corporation
AT28HC256N

High-speed Parallel EEPROM

ATMEL Corporation
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