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AT49BV320DT 데이터시트 PDF




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부품번호 AT49BV320DT 기능
기능 Flash Memory
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AT49BV320DT 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Features
Single Voltage Read/Write Operation: 2.65V to 3.6V
Access Time – 70 ns
Sector Erase Architecture
– Sixty-three 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
Fast Word Program Time – 10 µs
Fast Sector Erase Time – 100 ms
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 10 mA Active
– 15 µA Standby
VPP Pin for Write Protection and Accelerated Program Operation
WP Pin for Sector Protection
RESET Input for Device Initialization
Flexible Sector Protection
TSOP and CBGA Package Options
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Minimum 100,000 Erase Cycles
Common Flash Interface (CFI)
Green (Pb/Halide-free) Packaging
32-megabit
(2M x 16)
3-volt Only
Flash Memory
AT49BV320D
AT49BV320DT
1. Description
The AT49BV320D(T) is a 2.7-volt 32-megabit Flash memory organized as 2,097,152
words of 16 bits each. The memory is divided into 71 sectors for erase operations.
The device is offered in a 48-lead TSOP package and a 47-ball CBGA package. The
device has CE and OE control signals to avoid any bus contention. This device can be
read or reprogrammed using a single power supply, making it ideally suited for in-sys-
tem programming.
The device powers on in the read mode. Command sequences are used to place
the device in other operation modes such as program and erase. The device has
the capability to protect the data in any sector (see “Flexible Sector Protection” on
page 6).
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors
within the memory.
The VPP pin provides data protection. When the VPP input is below 0.4V, the program
and erase functions are inhibited. When VPP is at 1.65V or above, normal program
and erase operations can be performed. With VPP at 10.0V, the program (Dual-word
Program command) operation is accelerated.
3581C–FLASH–11/05




AT49BV320DT pdf, 반도체, 판매, 대치품
outputs are put in the high impedance state whenever CE or OE is high. This dual-line control
gives designers flexibility in preventing bus contention.
4.3 Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET input halts the
present device operation and puts the outputs of the device in a high impedance state. When a
high level is reasserted on the RESET pin, the device returns to the read mode, depending upon
the state of the control inputs.
4.4 Erase
Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a
logical “1”. The individual sectors can be erased by using the Sector Erase command.
4.4.1
Sector Erase
The device is organized into 71 sectors (SA0 - SA70) that can be individually erased. The Sector
Erase command is a two-bus cycle operation. The sector address and the D0H Data Input com-
mand are latched on the rising edge of WE. The sector erase starts after the rising edge of WE
of the second cycle provided the given sector has not been protected. The erase operation is
internally controlled; it will automatically time to completion. The maximum time to erase a sector
is tSEC. An attempt to erase a sector that has been protected will result in the operation terminat-
ing immediately.
4.5 Word Programming
Once a memory sector is erased, it is programmed (to a logical “0”) on a word-by-word basis.
Programming is accomplished via the Internal Device command register and is a two-bus cycle
operation. The device will automatically generate the required internal program pulses.
Any commands, except Read Status Register, Program Suspend and Program Resume, written
to the chip during the embedded programming cycle will be ignored. If a hardware reset hap-
pens during programming, the data at the location being programmed will be corrupted. Please
note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s
to “1”s. Programming is completed after the specified tBP cycle time. If the program status bit is a
“1”, the device was not able to verify that the program operation was performed successfully.
The status register indicates the programming status. While the program sequence executes,
status bit I/O7 is “0”.
4.6 VPP Pin
The circuitry of the AT49BV320D(T) is designed so that the device cannot be programmed or
erased if the VPP voltage is less that 0.4V. When VPP is at 1.65V or above, normal program and
erase operations can be performed. The VPP pin cannot be left floating.
4 AT49BV320D(T)
3581C–FLASH–11/05

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AT49BV320DT 전자부품, 판매, 대치품
AT49BV320D(T)
Table 4-2.
VPP
VCC/5V
VCC/5V
VCC/5V
VCC/5V
VCC/5V
VCC/5V
VCC/5V
VIL
Hardlock and Softlock Protection Configurations in Conjunction with WP
Erase/
Hard- Soft-
Prog
WP lock lock Allowed? Comments
0 0 0 Yes No sector is locked
001
No
Sector is Softlocked. The Unlock command
can unlock the sector.
011
No
Hardlock protection mode is enabled. The
sector cannot be unlocked.
1 0 0 Yes No sector is locked.
101
No
Sector is Softlocked. The Unlock command
can unlock the sector.
1
1
0
Yes
Hardlock protection mode is overridden and
the sector is not locked.
111
Hardlock protection mode is overridden and
No the sector can be unlocked via the Unlock
command.
xxx
No
Erase and Program Operations cannot be
performed.
Figure 4-1. Sector Locking State Diagram
UNLOCKED
LOCKED
WP = VIL = 0
[000]
60h/
D0h
60h/2Fh
60h/01h
[001]
60h/
2Fh
Power-Up/Reset
Default
[011]
Hardlocked
WP = VIH = 1
[110]
[100]
60h/D0h
60h/
D0h
60h/
01h
[111]
Hardlocked is disabled by
WP = VIH
60h/
2Fh
60h/
01h
60h/
2Fh
Power-Up/Reset
Default
[101]
3581C–FLASH–11/05
60h/D0h = Unlock Command
60h/01h = Softlock Command
60h/2Fh = Hardlock Command
Note: 1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector
is defined by the state of WP and the two bits of the sector-lock status D[1:0].
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