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AT49BV6416 데이터시트, 핀배열, 회로
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Features
64-megabit (4M x 16) Flash Memory
2.7V - 3.6V Read/Write
High Performance
– Asynchronous Access Time – 70 ns
– Page Mode Read Time – 20 ns
Sector Erase Architecture
– Eight 4K Word Sectors with Individual Write Lockout
– One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 200 ms
Four Plane Organization, Permitting Concurrent Read in Any of Three Planes not Being
Programmed/Erased
– Memory Plane A: 16M of Memory Including Eight 4K Word Sectors
– Memory Plane B: 16M of Memory Consisting of 32K Word Sectors
– Memory Plane C: 16M of Memory Consisting of 32K Word Sectors
– Memory Plane D: 16M of Memory Consisting of 32K Word Sectors
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 35 µA Standby
2.2V I/O Option Reduces Overall System Power
Data Polling and Toggle Bit for End of Program Detection
VPP Pin for Write Protection and Accelerated Program Operations
RESET Input for Device Initialization
TSOP Package
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
Green (Pb/Halide-free) Packaging Option
64-megabit
(4M x 16)
Page Mode
2.7-volt Flash
Memory
AT49BV6416
AT49BV6416T
1. Description
The AT49BV6416(T) is a 2.7-volt 64-megabit Flash memory. The memory is divided
into multiple sectors and planes for erase operations. The device can be read or
reprogrammed off a single 2.7V power supply, making it ideally suited for in-system
programming. The output voltage can be separately controlled down to 2.2V through
the VCCQ supply pin. The device can operate in the asynchronous or page read
mode.
The AT49BV6416(T) is divided into four memory planes. A read operation can occur
in any of the three planes which is not being programmed or erased. This concurrent
operation allows improved system performance by not requiring the system to wait for
a program or erase operation to complete before a read is performed. To further
increase the flexibility of the device, it contains an Erase Suspend and Program Sus-
pend feature. This feature will put the erase or program on hold for any amount of time
and let the user read data from or program data to any of the remaining sectors. There
is no reason to suspend the erase or program operation if the data to be read is in
another memory plane. The end of program or erase is detected by Data Polling or
toggle bit.
3451C–FLASH–2/05




AT49BV6416 pdf, 반도체, 판매, 대치품
3.5.2
Plane Erase
As a alternative to a full chip erase, the device is organized into four planes that can be individu-
ally erased. The plane erase command is a six-bus cycle operation. The plane whose address is
valid at the sixth falling edge of WE will be erased. The plane erase command does not alter the
data in protected sectors.
3.5.3
Sector Erase
As an alternative to a full chip erase or a plane erase, the device is organized into multiple sec-
tors that can be individually erased. The Sector Erase command is a six-bus cycle operation.
The sector whose address is valid at the sixth falling edge of WE will be erased provided the
given sector has not been protected.
3.6 Word Programming
The device is programmed on a word-by-word basis. Programming is accomplished via the
internal device command register and is a four-bus cycle operation. The programming address
and data are latched in the fourth cycle. The device will automatically generate the required
internal programming pulses. Please note that a “0” cannot be programmed back to a “1”; only
erase operations can convert “0”s to “1”s.
3.7 Flexible Sector Protection
The AT49BV6416(T) offers two sector protection modes, the Softlock and the Hardlock. The
Softlock mode is optimized as sector protection for sectors whose content changes frequently.
The Hardlock protection mode is recommended for sectors whose content changes infrequently.
Once either of these two modes is enabled, the contents of the selected sector is read-only and
cannot be erased or programmed. Each sector can be independently programmed for either the
Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Soft-
lock protection mode enabled.
3.7.1
Softlock and Unlock
The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to
the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To
enable the Softlock protection mode, a six-bus cycle Softlock command must be issued to the
selected sector.
3.7.2
Hardlock and Write Protect (WP)
The Hardlock sector protection mode operates in conjunction with the Write Protection (WP) pin.
The Hardlock sector protection mode can be enabled by issuing a six-bus cycle Hardlock soft-
ware command to the selected sector. The state of the Write Protect pin affects whether the
Hardlock protection mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be
unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector can be
unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.
4 AT49BV6416(T)
3451C–FLASH–2/05

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AT49BV6416 전자부품, 판매, 대치품
AT49BV6416(T)
The toggle bit status bit should be used in conjunction with the erase/program and VPP status bit
as shown in the algorithm in Figures 3-4 and 3-5 on page 10.
3.8.3
Erase/Program Status Bit
The device offers a status bit on I/O5 that indicates whether the program or erase operation has
exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to
verify that an erase or a word program operation has been successfully performed. The device
may also output a “1” on I/O5 if the system tries to program a “1” to a location that was previ-
ously programmed to a “0”. Only an erase operation can change a “0” back to a “1”. If a program
(Sector Erase) command is issued to a protected sector, the protected sector will not be pro-
grammed (erased). The device will go to a status read mode and the I/O5 status bit will be set
high, indicating the program (erase) operation did not complete as requested. Once the
erase/program status bit has been set to a “1”, the system must write the Product ID Exit com-
mand to return to the read mode. The erase/program status bit is a “0” while the erase or
program operation is still in progress. Please see “Status Bit Table” on page 11 for more details.
3.8.4
VPP Status Bit
The AT49BV6416(T) provides a status bit on I/O3 that provides information regarding the volt-
age level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is
not high enough to perform the desired operation successfully, the I/O3 status bit will be a “1”.
Once the VPP status bit has been set to a “1”, the system must write the Product ID Exit com-
mand to return to the read mode. On the other hand, if the voltage level is high enough to
perform a program or erase operation successfully, the VPP status bit will output a “0”. Please
see “Status Bit Table” on page 11 for more details.
3.9 Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector erase operation and then
program or read data from a different sector within the same plane. Since this device has a mul-
tiple plane architecture, there is no need to use the erase suspend feature while erasing a sector
when you want to read data from a sector in another plane. After the Erase Suspend command
is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the
erase operation has been suspended, the plane that contains the suspended sector enters the
erase-suspend-read mode. The system can then read data or program data to any other sector
within the device. An address is not required during the Erase Suspend command. During a sec-
tor erase suspend, another sector cannot be erased. To resume the sector erase operation, the
system must write the Erase Resume command. The Erase Resume command is a one-bus
cycle command, which does require the plane address. The device also supports an erase sus-
pend during a complete chip erase. While the chip erase is suspended, the user can read from
any sector within the memory that is protected. The command sequence for a chip erase sus-
pend and a sector erase suspend are the same.
3.10
Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command is
given, the device requires a maximum of 10 µs to suspend the programming operation. After the
programming operation has been suspended, the system can then read from any other word
within the device. An address is not required during the program suspend operation. To resume
the programming operation, the system must write the Program Resume command. The
program suspend and resume are one-bus cycle commands. The command sequence for the
3451C–FLASH–2/05
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