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PDF AT49F040B Data sheet ( Hoja de datos )

Número de pieza AT49F040B
Descripción Flash Memory
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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Features
Single Supply for Read and Write: 4.5 to 5.5V
Fast Read Access Time – 55 ns
Internal Program Control and Timer
Flexible Sector Architecture
– One 16K Bytes Boot Sector with Programming Lockout
– Two 8K Bytes Parameter Sectors
– Eight Main Memory Sectors (One 32K Bytes, Seven 64K Bytes)
Fast Erase Cycle Time – 8 Seconds
Byte-by-Byte Programming – 12 µs/Byte Typical
Hardware Data Protection
DATA Polling or Toggle Bit for End of Program Detection
Low Power Dissipation
– 20 mA Active Current
– 25 µA CMOS Standby Current
Minimum 100,000 Write Cycles
4-megabit
(512K x 8)
5-volt Only
Flash Memory
1. Description
The AT49F040B is a 5-volt-only in-system reprogrammable Flash Memory. Its
4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
55 ns with power dissipation of just 110 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 25 µA. To
allow for simple in-system reprogrammability, the AT49F040B does not require high
input voltages for programming. Five-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to
reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus conten-
tion. Reprogramming the AT49F040B is performed by erasing a sector of data and
then programming on a byte by byte basis. The byte programming time is a fast 12 µs.
The end of a program or erase cycle can be optionally detected by the DATA polling
or toggle bit feature. Once the end of a byte program cycle has been detected, a new
access for a read or program can begin. The typical number of program and erase
cycles is in excess of 100,000 cycles.
The device is erased by executing a chip erase or a sector erase command sequence;
the device internally controls the erase operations. The memory array of the
AT49F040B is organized into two 8K byte parameter sectors, eight main memory sec-
tors, and one boot sector.
The device has the capability to protect the data in the boot sector; this feature is
enabled by a command sequence. The 16K-byte boot sector includes a reprogram-
ming lock out feature to provide data integrity. The boot sector is designed to contain
user secure code, and when the feature is enabled, the boot sector is permanently
protected from being reprogrammed.
AT49F040B
3606A–FLASH–12/05

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AT49F040B pdf
AT49F040B
4.6 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
4.7 Data Polling
The AT49F040B features DATA polling to indicate the end of a program or erase cycle. During a
program cycle an attempted read of the last byte loaded will result in the complement of the
loaded data on I/O7. Once the program cycle has been completed, true data is valid on all out-
puts and the next cycle may begin. DATA polling may begin at any time during the program
cycle. During a chip or sector erase operation, an attempt to read the device will give a “0” on
I/O7. Once the erase operation is completed, a “1” will be read from I/O7. The Data Polling sta-
tus bit must be used in conjunction with the erase/program status bit as shown in the algorithm
in Figure 4-1 on page 6.
4.8 Toggle Bit
In addition to DATA polling, the AT49F040B provides another method for determining the end of
a program or erase cycle. During a program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle. The toggle bit status bit should be used in conjunction
with the erase/program status bit shown in the algorithm in Figure 4-2 on page 6.
4.9 Erase/Program Status Bit
The device offers a status bit on I/O5, which indicates whether the program or erase operation
has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable
to verify that an erase or a byte program operation has been successfully performed. If a pro-
gram (Sector Erase) command is issued to the boot sector and the boot sector programming
lockout feature is enabled, the boot sector will not be programmed (erased), and the device will
go into the read mode. Once the erase/program status bit has been set to a “1”, the system must
write the Product ID Exit command to return to the read mode. The erase/program status bit is a
“0” while the erase or program operation is still in progress.
4.10
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49F040B in the following
ways: (a) Program inhibit: holding any one of OE low, CE high or WE high inhibits program
cycles. (b) Noise filter: pulses of less than 10 ns (typical) on the WE or CE inputs will not initiate
a program cycle.
3606A–FLASH–12/05
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AT49F040B arduino
13. Input Test Waveform and Measurement Level
AC
DRIVING
LEVELS
3.0V
0.0V
1.5V
AC
MEASUREMENT
LEVEL
tR, tF < 5 ns
14. Output Load Test
5.0V
1.8K
1.3K
OUTPUT
PIN
30 pF
15. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
CIN
COUT
Note:
46
8 12
1. This parameter is characterized and is not 100% tested.
Units
pF
pF
AT49F040B
Conditions
VIN = 0V
VOUT = 0V
3606A–FLASH–12/05
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