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PDF ISL1220 Data sheet ( Hoja de datos )
| Número de pieza | ISL1220 | |
| Descripción | I2C Real Time Clock/Calendar | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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ISL1220
® I2C® Real Time Clock/Calendar with Frequency Output
Data Sheet
June 22, 2006
FN6315.0
Low Power RTC with 8 Bytes of Battery
Backed SRAM and Separate FOUT
The ISL1220 device is a low power real time clock with
timing and crystal compensation, clock/calendar, power fail
indicator, periodic or polled alarm, intelligent battery backup
switching, battery-backed user SRAM and separate FOUT
and IRQ outputs.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Ordering Information
PART
NUMBER
(Note)
PART
VDD
MARKING RANGE
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
ISL1220IUZ 1220Z 2.7V to 5.5V -40 to +85 10 Ld MSOP
ISL1220IUZ-T 1220Z
2.7V to 5.5V -40 to +85 10 Ld MSOP
Tape and Reel
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL1220
(10 LD MSOP)
TOP VIEW
X1 1
X2 2
VBAT 3
GND 4
NC 5
10 VDD
9 IRQ
8 SCL
7 SDA
6 FOUT
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month, and Year
• Frequency Output pin
- 15 Selectable Output Frequencies
• Single Alarm with Separate Interrupt pin
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Automatic Backup to Battery or Super Cap
• Power Failure Detection
• On-Chip Oscillator Compensation
• 8 Bytes Battery-Backed User SRAM
• I2C Interface
- 400kHz Data Transfer Rate
• 400nA Battery Supply Current
• Small Package Option
- 10 Ld MSOP Package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
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ISL1220
SDA vs SCL Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
Symbol Table
WAVEFORM
INPUTS
Must be steady
OUTPUTS
Will be steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not Known
N/A Center Line is
High Impedance
5 FN6315.0
June 22, 2006
5 Page 
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ISL1220
Real Time Clock Registers
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 0 to 59,
HR (Hour) can either be a 12-hour or 24-hour mode, DT
(Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99,
and DW (Day of the Week) is 0 to 6.
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-
2-… The assignment of a numerical value to a specific day
of the week is arbitrary and may be decided by the system
software designer. The default value is defined as “0”.
24 HOUR TIME
If the MIL bit of the HR register is “1”, the RTC uses a
24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour
format and HR21 bit functions as an AM/PM indicator with a
“1” representing PM. The clock defaults to 12-hour format
time with HR21 = “0”.
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year, the year 2100 is not. The ISL1220
does not correct for the leap year in the year 2100.
Control and Status Registers
Addresses [07h to 0Bh]
The Control and Status Registers consist of the Status
Register, Interrupt and Alarm Register, Analog Trimming and
Digital Trimming Registers.
Status Register (SR)
The Status Register is located in the memory map at
address 07h. This is a volatile register that provides either
control or status of RTC failure, battery mode, alarm trigger,
write protection of clock counter, crystal oscillator enable and
auto reset of status bits.
ADDR 7
TABLE 2. STATUS REGISTER (SR)
6 5 4 32
1
0
07h ARST XTOSCB reserved WRTC reserved ALM BAT RTCF
Default 0
0
0 0 0 00 0
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL1220 internally) when the
device powers up after having lost all power to the device.
The bit is set regardless of whether VDD or VBAT is applied
first. The loss of only one of the supplies does not set the
RTCF bit to “1”. The first valid write to the RTC section after
a complete power failure resets the RTCF bit to “0” (writing
one byte is sufficient).
BATTERY BIT (BAT)
This bit is set to a “1” when the device enters battery backup
mode. This bit can be reset either manually by the user or
automatically reset by enabling the auto-reset bit (see ARST
bit). A write to this bit in the SR can only set it to “0”, not “1”.
ALARM BIT (ALM)
These bits announce if the alarm matches the real time
clock. If there is a match, the respective bit is set to “1”. This
bit can be manually reset to “0” by the user or automatically
reset by enabling the auto-reset bit (see ARST bit). A write to
this bit in the SR can only set it to “0”, not “1”.
NOTE: An alarm bit that is set by an alarm occurring during an SR
read operation will remain set after the read operation is complete.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this bit
is “0”. Upon initialization or power up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle.
CRYSTAL OSCILLATOR ENABLE BIT (XTOSCB)
This bit enables/disables the internal crystal oscillator. When
the XTOSCB is set to “1”, the oscillator is disabled, and the
X1 pin allows for an external 32kHz signal to drive the RTC.
The XTOSCB bit is set to “0” on power-up.
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the BAT and
ALM status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the respective
status register (with a valid STOP condition). When the
ARST is cleared to “0”, the user must manually reset the
BAT and ALM bits.
Interrupt Control Register (INT)
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR 7 6
5
4 321
0
08h IM ALME LPMODE FOBATB FO3 FO2 FO1 FO0
Default 0 0
0
0 0000
The interrupt control register contains Frequency Output,
Alarm, and Battery switchover control bits.
11 FN6315.0
June 22, 2006
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL1220.PDF ] | |
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