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ATAR080 데이터시트 PDF




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부품번호 ATAR080 기능
기능 Low-current Microcontroller
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ATAR080 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Features/Benefits
Very Low Power Consumption in Active, Power-down and Sleep Mode
2-Kbyte ROM, 256 × 4-bit RAM
12 Bi-directional I/Os
Up to 6 External/Internal Interrupt Sources
Multifunction Timer/Counter
Programmable System-clock with Prescaler and Five Different Clock Sources
Wide Supply-voltage Range (1.8 V to 6.5 V)
Very Low Sleep Current (< 1 µA)
Synchronous Serial Interface (2-wire, 3-wire)
Watchdog, POR and Brown-out Function
Voltage Monitoring Inclusive Lo_BAT Detection
Flash Controller ATAM893 available (SSO20)
Description
The ATAR080 is a member of Atmel’s family of 4-bit single-chip microcontrollers. It
contains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction
timer/counter with modulator function, voltage supervision, interval timer with watch-
dog function and a sophisticated on-chip clock generation with external clock input,
integrated RC-, 32-kHz and 4-MHz crystal-oscillators.
Figure 1. Block Diagram
VSS VDD
NRST/
OSC1 OSC2
Low-current
Microcontroller
for Wireless
Communication
ATAR080
BP20/NTE
BP21
BP22
BP23
Brown-out
protect RESET
Voltage Monitor
External input
VMI
RC Crystal External
oscillators oscillators clock input
Clock management
ROM
RAM
2 K × 8 bit 256 × 4 bit
MARC4
4-bit CPU core
I/O bus
UTCM
Timer 1
interval- and
watchdog timer
Timer 2
8/12-bit timer
with modulator
SSI
Serial interface
T2I
T2O
SD
SC
Data direction +
alternate function
Port 4
Data direction +
interrupt control
Port 5
BP40 BP42
INT3 T2O
SC
BP41 BP43
VMI INT3
T2I SD
BP50 BP52
INT6 INT1
BP51 BP53
INT6 INT1
Rev. 4675D–4BMCU–12/04




ATAR080 pdf, 반도체, 판매, 대치품
Components of MARC4
Core
Figure 4. ROM Map
7FFh
ROM
(2 K × 8 bit)
1FFh
000h
Zero page
1F8h
1F0h
1E8h
1E0h
020h
018h
010h
008h
000h
Zero
page
1E0h
1C0h
180h
140h
100h
0C0h
080h
040h
008h
000h
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
$RESET
$AUTOSLEEP
ROM
RAM
Expression Stack
Return Stack
The core contains ROM, RAM, ALU, program counter, RAM address registers, instruc-
tion decoder and interrupt controller. The following sections describe each functional
block in more detail.
The program memory (ROM) is mask programmed with the customer application pro-
gram during fabrication of the microcontroller. The 2 Kbyte ROM size is addressed by a
12-bit wide program counter. An additional 1-Kbyte of ROM exists, which is reserved for
quality control self-test software The lowest user ROM address segment is taken up by
a 512-byte Zero page which contains predefined start addresses for interrupt service
routines and special subroutines accessible with single byte instructions (SCALL).
The corresponding memory map is shown in Figure 4. Look-up tables of constants can
also be held in ROM and are accessed via the MARC4's built-in table instruction.
The ATAR080 contains 256 × 4-bit wide static random access memory (RAM), which is
used for the expression stack. The return stack and data memory are used for variables
and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers
SP, RP, X and Y.
The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All
arithmetic, I/O and memory reference operations take their operands, and return their
results to the expression stack. The MARC4 performs the operations with the top of
stack items (TOS and TOS-1). The TOS register contains the top element of the expres-
sion stack and works in the same way as an accumulator. This stack is also used for
passing parameters between subroutines and as a scratch pad area for temporary stor-
age of data.
The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for
storing return addresses of subroutines, interrupt routines and for keeping loop index
counts. The return stack can also be used as a temporary storage area.
The MARC4 instruction set supports the exchange of data between the top elements of
the expression stack and the return stack. The two stacks within the RAM have a user
definable location and maximum depth.
4 ATAR080
4675D–4BMCU–12/04

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ATAR080 전자부품, 판매, 대치품
ALU
I/O Bus
Instruction Set
Interrupt Structure
ATAR080
Figure 7. ALU Zero-address Operations
RAM
SP TOS-1
TOS-2
TOS-3
TOS-4
TOS
ALU
CCR
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top
two elements of the expression stack (TOS and TOS-1) and returns the result to the
TOS. The ALU operations affect the carry/borrow and branch flag in the condition code
register (CCR).
The I/O ports and the registers of the peripheral modules are I/O mapped. All communi-
cation between the core and the on-chip peripherals take place via the I/O bus and the
associated I/O control. With the MARC4 IN and OUT instructions, the I/O bus allows a
direct read or write access to one of the 16 primary I/O addresses. More about the I/O
access to the on-chip peripherals is described in the section “Peripheral Modules”. The
I/O bus is internal and is not accessible by the customer on the final microcontroller
device, but it is used as the interface for the MARC4 emulation (see section
“Emulation”).
The MARC4 instruction set is optimized for the high level programming language
qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to
generate a fast and compact program code. The CPU has an instruction pipeline allow-
ing the controller to prefetch an instruction from ROM at the same time as the present
instruction is being executed. The MARC4 is a zero address machine, the instructions
containing only the operation to be performed and no source or destination address
fields. The operations are implicitly performed on the data placed on the stack. There
are one and two byte instructions which are executed within 1 to 4 machine cycles. A
MARC4 machine cycle is made up of two system clock cycles (SYSCL). Most of the
instructions are only one byte long and are executed in a single machine cycle. For
more information refer to the “MARC4 Programmer's Guide”.
The MARC4 can handle interrupts with eight different priority levels. They can be gener-
ated from the internal and external interrupt sources or by a software interrupt from the
CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the
service routine in the ROM (see Table 1 on page 9). The programmer can postpone the
processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt
occurrence will still be registered, but the interrupt routine only starts after the I flag is
set. All interrupts can be masked, and the priority individually software configured by
programming the appropriate control register of the interrupting module (see section
“Peripheral Modules”).
4675D–4BMCU–12/04
7

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부품번호상세설명 및 기능제조사
ATAR080

Low-current Microcontroller

ATMEL Corporation
ATMEL Corporation

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