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부품번호 EPM7512B 기능
기능 (EPM7000B) Programmable Logic Device
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EPM7512B 데이터시트, 핀배열, 회로
www.DataSheet4U.com
September 2003, ver. 3.4
®
MAX 7000B
Programmable Logic
Device
Data Sheet
Features...
f
High-performance 2.5-V CMOS EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX®) architecture (see Table 1)
– Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V
MAX 7000A device families
– High-density PLDs ranging from 600 to 10,000 usable gates
– 3.5-ns pin-to-pin logic delays with counter frequencies in excess
of 303.0 MHz
Advanced 2.5-V in-system programmability (ISP)
– Programs through the built-in IEEE Std. 1149.1 Joint Test Action
Group (JTAG) interface with advanced pin-locking capability
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in-system programming
– ISP circuitry compliant with IEEE Std. 1532
For information on in-system programmable 5.0-V MAX 7000S or 3.3-V
MAX 7000A devices, see the MAX 7000 Programmable Logic Device Family
Data Sheet or the MAX 7000A Programmable Logic Device Family Data Sheet.
Table 1. MAX 7000B Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
tPD (ns)
tSU (ns)
tFSU (ns)
tCO1 (ns)
fCNT (MHz)
EPM7032B
600
32
2
36
3.5
2.1
1.0
2.4
303.0
EPM7064B
1,250
64
4
68
3.5
2.1
1.0
2.4
303.0
EPM7128B
2,500
128
8
100
4.0
2.5
1.0
2.8
243.9
EPM7256B
5,000
256
16
164
5.0
3.3
1.0
3.3
188.7
EPM7512B
10,000
512
32
212
5.5
3.6
1.0
3.7
163.9
Altera Corporation
DS-MAX7000B-3.4
1




EPM7512B pdf, 반도체, 판매, 대치품
MAX 7000B Programmable Logic Device Data Sheet
Table 3. MAX 7000B Maximum User I/O Pins Note (1)
Device
44-Pin
PLCC
44-Pin
TQFP
48-Pin
TQFP
(2)
49-Pin
0.8-mm
Ultra
FineLine
BGA (3)
100-
Pin
TQFP
100-Pin
FineLine
BGA (4)
144-
Pin
TQFP
169-Pin
0.8-mm
Ultra
FineLine
BGA (3)
208-
Pin
PQFP
256- 256-Pin
Pin FineLine
BGA BGA (4)
EPM7032B 36 36 36
36
EPM7064B 36 36 40 41 68 68
EPM7128B
41 84 84 100 100
100
EPM7256B
84
120 141 164
164
EPM7512B
120 141 176 212 212
Notes:
(1) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O
pins become JTAG pins.
(2) Contact Altera for up-to-date information on available device package options.
(3) All 0.8-mm Ultra FineLine BGA packages are footprint-compatible via the SameFrameTM pin-out feature. Therefore,
designers can design a board to support a variety of devices, providing a flexible migration path across densities
and pin counts. Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on
page 14 for more details.
(4) All FineLine BGA packages are footprint-compatible via the SameFrame pin-out feature. Therefore, designers can
design a board to support a variety of devices, providing a flexible migration path across densities and pin counts.
Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 14 for more
details.
MAX 7000B devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000B architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
MAX 7000B devices contain 32 to 512 macrocells that are combined into
groups of 16 macrocells, called logic array blocks (LABs). Each macrocell
has a programmable-AND/fixed-OR array and a configurable register with
independently programmable clock, clock enable, clear, and preset
functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms to provide up to 32 product terms
per macrocell.
4 Altera Corporation

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EPM7512B 전자부품, 판매, 대치품
MAX 7000B Programmable Logic Device Data Sheet
Macrocells
The MAX 7000B macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists of
three functional blocks: the logic array, the product-term select matrix,
and the programmable register. Figure 2 shows the MAX 7000B
macrocell.
Figure 2. MAX 7000B Macrocell
LAB Local Array
Parallel Logic
Expanders
(from other
macrocells)
Product-
Term
Select
Matrix
Global Global
Clear Clocks
2
From
I/O pin
Fast Input Programmable
Select
Register
Clock/
Enable
Select
Register
Bypass
PRN
D/T Q
ENA
CLRN
To I/O
Control
Block
VCC
Clear
Select
36 Signals
from PIA
16 Expander
Product Terms
Shared Logic
Expanders
To PIA
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
Altera Corporation
7

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