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ZL50110 데이터시트 PDF




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부품번호 ZL50110 기능
기능 (ZL50110 / ZL50114) CESoP Processors
제조업체 Zarlink Semiconductor
로고 Zarlink Semiconductor 로고


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ZL50110 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ZL50110/11/14
128, 256 and 1024 Channel CESoP
Processors
Data Sheet
Features
General
• Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
• On chip timing & synchronization recovery across
a packet network
• Grooming capability for Nx64 Kbps trunking
Circuit Emulation Services
• Complies with ITU-T recommendation Y.1413
• Complies with IETF PWE3 draft standards for
CESoPSN and SAToP
• Complies with CESoP draft IAs for MEF and MFA
• Structured, synchronous CESoP with clock
recovery
• Unstructured, asynchronous CESoP, with integral
per stream clock recovery
TDM Interfaces
• Up to 32 T1/E1, 8 J2, 2 T3/E3 or 1 STS-1 ports
• H.110, H-MVIP, ST-BUS backplanes
• Up to 1024 bi-directional 64 Kbps channels
October 2005
Ordering Information
ZL50110GAG
ZL50111GAG
ZL50114GAG
552 PBGA
552 PBGA
552 PBGA
Trays, Bake & Drypack
Trays, Bake & Drypack
Trays, Bake & Drypack
-40°C to +85°C
• Direct connection to LIUs, framers, backplanes
• Dual reference Stratum 3, 4 and 4E DPLL for
synchronous operation
Network Interfaces
• Up to 3 x 100 Mbps MII Fast Ethernet or Dual
Redundant 1000 Mbps GMII/TBI Ethernet
Interfaces
System Interfaces
• Flexible 32 bit host CPU interface (Motorola
PowerQUICCcompatible)
• On-chip packet memory for self-contained
operation, with buffer depths of over 16 ms
• Up to 8 Mbytes of off-chip packet memory,
supporting buffer depths of over 128 ms
TDM
Interface
(LIU, Framer, Backplane)
Per Port DCO for
Clock Recovery
Multi-Protocol
Packet
Processing
Engine
PW, RTP, UDP,
IPv4, IPv6, MPLS,
ECID, VLAN, User
Defined, Others
Triple
Packet
Interface
MAC
(MII, GMII, TBI)
On Chip Packet Memory
(Jitter Buffer Compensation for 16-128 ms of Packet Delay Variation)
Dual Reference
Stratum 3 DPLL
Host Processor
Interface
External Memory
Interface (optional)
32-bit Motorola compatible
DMA for signaling packets
ZBT-SRAM
(0 - 8 Mbytes)
Figure 1 - ZL50110/11/14 High Level Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.




ZL50110 pdf, 반도체, 판매, 대치품
ZL50110/11/14
Data Sheet
Device Line Up
There are three products within the ZL50110/11/14 family, with capacity as shown in the following table:
Device
TDM Interfaces
Ethernet Packet I/F
ZL50114
ZL50110
ZL50111
4 T1, 4 E1, or 1 J2 streams or
4 MVIP/ST-BUS streams at 2.048 Mbps or
1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
Dual 100 Mbps MII or
Dual Redundant 1000 Mbps GMII/TBI
8 T1, 8 E1 or 2 J2 streams or
8 MVIP/ST-BUS streams at 2.048 Mbps or
2 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
Dual 100 Mbps MII or
Dual Redundant 1000 Mbps GMII/TBI
32 T1, 32 E1, 8 J2, 2 T3, 2 E3 or 1 STS-1 streams or
32 MVIP/ST-BUS streams at 2.048 Mbps or
8 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
Triple 100 Mbps MII or
Dual Redundant 1000 Mbps GMII/TBI or
Single 100 Mbps MII and Single 1000
Mbps GMII/TBI
Table 1 - Capacity of Devices in the ZL50110/11/14 Family
4
Zarlink Semiconductor Inc.

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ZL50110 전자부품, 판매, 대치품
ZL50110/11/14
Data Sheet
Table of Contents
11.10 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.0 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
13.0 Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
13.1 High Speed Clock & Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
13.1.1 External Memory Interface - special considerations during layout. . . . . . . . . . . . . . . . . . . . . . . . . 95
13.1.2 GMAC Interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.1.3 TDM Interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.1.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.2 CPU TA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.3 Mx_LINKUP_LED Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.0 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
14.1 External Standards/Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
14.2 Zarlink Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
15.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7
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관련 데이터시트

부품번호상세설명 및 기능제조사
ZL50110

(ZL50110 / ZL50114) CESoP Processors

Zarlink Semiconductor
Zarlink Semiconductor
ZL50111

(ZL50110 / ZL50114) CESoP Processors

Zarlink Semiconductor
Zarlink Semiconductor

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