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PDF ATA6286 Data sheet ( Hoja de datos )
| Número de pieza | ATA6286 | |
| Descripción | (ATA6285 / ATA6286) TPMS Control and Transmitter IC | |
| Fabricantes | ATMEL Corporation | |
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Features
• Programmable AVR® 8-bit Flash Microcontroller Transmitter IC
• Frequency: 315 MHz (ATA6285) and 433 MHz (ATA6286)
• Support ASK/FSK Modulation with Integrated FSK Switch
• 6 dBm Output Power with Typically 8.5 mA Active Current Consumption in
Transmission Mode
• Low-power Microcontroller Requires Typically 0.6 µA Sleep Current with Active Interval
Timer
• Interfaces for Simple Capacitive Sensors (2 pF to 6 pF)
• One Interface Can Be Configured for Motion Wake-up (3 pF to 5 pF)
• Typically 25 mbar ADC Resolution for Pressure Measurement with Dedicated Sensor
Type
• Low-power Measurement Mode for Directly Connected Capacitive Sensors Typically
200 µA at 1 MHz System Clock
• Programmable 125 kHz Wake-up Receiver Channel with Typically 1.7 µA Current
Consumption in Listing Mode
• 2V to 3.6V Operation Voltage for Single Li-cell Power Supply
• –40°C to +125°C Operation Temperature and –40°C to +150°C Storage Temperature
• Less then 10 External Passive Components
• QFN32 (5 mm × 5 mm) Package
1. Description
ATA6285 and ATA6286 are highly integrated smart RF micro transmitter ICs for
315 MHz and 433 MHz, suited for ASK and FSK with typically 20 Kbits/s data rate in
Manchester mode. The devices combine the functionality of the RF transmitter ICs
ATA5756/ATA5757 with the programmable low-power AVR 8-bit Flash microcontroller
in a single QFN32 package (5 mm × 5 mm). The ATA6285 and ATA6286 include a
dedicated ADC interface for simple capacitive sensors as well as an on-chip tempera-
ture sensor. Three sensor interfaces are available for a capacitive range of 2 pF to
16 pF, where one channel can be configured as motion wake-up in the range of 3 pF
to 5 pF. The ICs are suited for use in tire pressure monitoring (TPMS) sensor gauges
in combination with external sensor devices.
The programmable AVR 8-bit Flash microcontroller includes 8 Kbytes of in-system
self-programmable Flash memory and an 320-Bytes EEPROM, thus allowing the sys-
tem integrator to install field-programmable firmware to enable system flexibility on
different platforms. ATA6285 and ATA6286 can be configured to guarantee extremely
low power consumption in sleep mode and measurement mode. They also include a
programmable 125 kHz wake-up receiver channel for extremely low current consump-
tion in listening mode. The ICs are designed for use in applications with typically less
then 10 passive components: one external crystal for the sensor gauge, several
capacitors, a single LiMnO2 battery coin cell, a single-ended antenna for the data
transmission and an LF ferrite coil for the wake-up channel. ATA6285 and ATA6286
support TPMS-specific low-current modes even with an active brown-out detection
and an interval timer.
TPMS Control
and Transmitter
IC
ATA6285
ATA6286
Summary
Preliminary
NOTE: This is a summary document.
The complete document is available
under NDA. For more information,
please contact your local Atmel sales
office.
4958AS–AUTO–09/06
DataSheet4 U .com
1 page  
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ATA6285/ATA6286 [Preliminary]
Table 2-2. Pin Description (Continued)
Pin Number
Pin Name
Alternate
Function 1
19 LF1
–
20 LF2
–
21 VCC
22 PC2
–
–
23 PC1 CLKO
24 PC0 ECIN0
25 PD0 T2ICP
26 PD1 T3I
27 PB0 T3ICP
28 GND
–
29 GND
–
Inter-die(1)
PD3
INT1
Inter-die(1)
PD4
ECIN1
Inter-die(1)
PD5
T2O1
Inter-die(1)
PD6
T2O2
30 PD7 SDIN
31 PD2 INT0
32 PB3 MOSI
Note: 1. Internal inter-die connection of the MCP
Alternate
Function 2
–
–
–
PCINT10
PCINT9
PCINT8
PCINT16
PCINT17
PCINT0
–
–
PCINT19
PCINT20
PCINT21
PCINT22
PCINT23
PCINT18
PCINT3
Function
LF-receiver input 1
LF-receiver input 2
Power supply voltage (VCC + AVCC)
-
System clock output
External Clock input 0
Timer2 external input capture
Timer3 external input clock
Timer3 external input capture
Power supply ground
Power supply ground
External Interrupt 1 →Inter-die
connection
External Clock input 1 →Inter-die
connection
Timer2 Modulator output 1 →
Inter-die connection
Timer2 Modulator output 2 →
Inter-die connection
SSI –Serial Data Input
External interrupt input 0
SPI
Comment
Port C2
Port C1
Port C1
Port D0
Port D1
Port B0
Port D2
Port D4
Port D5
Port D6
Port D7
Port D2
Port B3
2.5 Pin Names
2.5.1 VCC
Supply voltage
2.5.2 GND
Ground
2.5.3
Port B (PB7..0)
Port B is a 5(8)-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PB7, PB6 and PB2 ports are only used as internal I/O ports for inter-die connections. The Port B
output buffers have symmetrical drive characteristics with both high sink and source current
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmegaT.
4958AS–AUTO–09/06
DataSheet4 U .com
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ATA6285/ATA6286 [Preliminary]
4.4 General Description
This fully integrated PLL transmitter allows the design of simple, low-cost RF miniature transmit-
ters for TPM and RKE applications. The VCO is locked to 24 × fXTAL/32 x fXTAL for
ATA6285/ATA6286. Thus, a 13.125 MHz/13.56 MHz crystal is needed for a 315 MHz/
433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated.
The XTO is a series resonance (current mode) oscillator. Only one capacitor and a crystal con-
nected in series to GND are needed as external elements in an ASK system. The internal FSK
switch, together with a second capacitor, can be used for FSK modulation. The crystal oscillator
needs typically 0.6 ms until the CLK output is activated if a crystal as defined in the electrical
characteristics is used (e.g., TPM crystal). For most crystals used in RKE systems, a shorter
time will result.
The CLK output is switched on if the amplitude of the current flowing through the crystal has
reached 35% to 80% of its final value. This is synchronized with the 1.64 MHz/1.69 MHz CLK
output. As a result, the first period of the CLK output is always a full period. The PLL is then
locked < 250 µs after CLK output activation. This means an additional wait time of ≥ 250 µs is
necessary before the PA can be switched on and the data transmission can start. This results in
a significantly lower time of about 0.85 ms between enabling the ATA6285/ATA6286 and the
beginning of the data transmission which saves battery power especially in tire pressure moni-
toring systems.
The power amplifier is an open-collector output delivering a current pulse which is nearly inde-
pendent from the load impedance and therefore the output power can be controlled via the
connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50Ω. A high
power efficiency for the power amplifier results if an optimized load impedance of
ZLoad, opt = 380Ω + j340Ω (ATA6285) at 315 MHz and ZLoad, opt = 280Ω + j310Ω (ATA6286) at
433.92 MHz is used at the 3V supply voltage.
4.5 Functional Description
If ASK = Low, FSK = Low and ENABLE = open or Low, the circuit is in power-down mode con-
suming only a very small amount of current so that a lithium cell used as power supply can work
for many years.
If the ENABLE pin is left open, ENABLE is the logical OR operation of the ASK and FSK input
pins. This means, the IC can be switched on by either the FSK of the ASK input.
If the ENABLE pin is Low and ASK or FSK are High, the IC is in idle mode where the PLL, XTO
and power amplifier are off and the microcontroller ports controlling the ASK and FSK inputs can
be used to control other devices. This can help to save ports on the microcontroller in systems
where other devices with 3-wire interface are used.
With FSK = High and ASK = Low and ENABLE = open or High, the PLL and the XTO are
switched on and the power amplifier is off. When the amplitude of the current through the crystal
has reached 35% to 80% of its final amplitude, the CLK driver is automatically activated. The
CLK output stays Low until the CLK driver has been activated. The driver is activated synchro-
nously with the CLK output frequency, hence, the first pulse on the CLK output is a complete
period. The PLL is then locked within < 250 µs after the CLK driver has been activated, and the
transmitter is then ready for data transmission.
4958AS–AUTO–09/06
DataSheet4 U .com
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ATA6286.PDF ] | |
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| Número de pieza | Descripción | Fabricantes |
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