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PDF AMD-766 Data sheet ( Hoja de datos )
| Número de pieza | AMD-766 | |
| Descripción | Peripheral Bus Controller | |
| Fabricantes | AMD | |
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23167B - March 2001
Preliminary Information
AMD-766TM Peripheral Bus Controller Data Sheet
AMD-766TM
Peripheral Bus Controller
Data Sheet
1
1 page  
23167B – March 2001
Preliminary Information
AMD-766TM Peripheral Bus Controller Data Sheet
1 Overview
The AMD-766 peripheral bus controllerTM is an integrated circuit (IC), developed by AMD, to be the system
Southbridge component of personal computer chipsets. The AMD-766 peripheral bus controller (the IC) connects to
a host memory controller through the PCI bus.
1.1 Features
• PCI interface (PCI specification revision 2.2
compliant).
• LPC bus to connect peripherals such as super
IO and BIOS.
• Partial ISA bus.
• 8 bits wide.
• Support for Flash BIOS.
• Enhanced IDE controller.
• Support for two dual-drive ports.
• PIO modes 0-4.
• Multi-word DMA.
• UDMA modes up to ATA-100.
• OHCI-based USB host controller with support
for four ports.
• Serial IRQ protocol.
• ACPI-compliant power management logic.
• Programmable C2, C3, power-on-
suspend, suspend to RAM, suspend to
disk, and soft off states.
• Throttling.
• Hardware traps.
• System inactivity timer.
• 32 general-purpose IO (GPIO) pins (some are
multiplexed with other hard-wired functions).
• Privacy/security logic (ROM access control).
• Legacy logic.
• Programmable interrupt controller.
• Programmable interval timer.
• DMA controller (for LPC bus).
• Legacy ports.
• IOAPIC controller.
• Real-time clock.
• 256 bytes of CMOS RAM.
• Battery-powered.
• ACPI-compliant extensions.
• SMBus controller with one SMBus port.
• 272-pin BGA package.
• 3.3-volt core and output drivers; 5-volt
tolerant input buffers.
The IC is intended to fit into the traditional Southbridge position on PC-compatible platforms.
System
Memory
PCI bus
Memory
Controller
Host
IDE ports
USB ports
Super I/O
Peripheral
Bus
Controller
BIOS
ROM
LPC bus
ISA bus
5
5 Page 
23167B – March 2001
Preliminary Information
AMD-766TM Peripheral Bus Controller Data Sheet
3.6 System Management Signals
This group includes all the GPIO pins, many of which are multiplexed with other functions. The default function of
GPIO pins after reset is specified by PM[FF:F4 and D3:C0]. When programmed as GPIOs, these pins are capable of
being programmed to be inputs or push-pull outputs. GPIO pins remain functional during sleep states (if they are
powered).
Pin name and description
IO cell Power During Post POS
type plane Reset Reset
C32KHZ. 32.768 kHz clock output. This pin may also be configured as Output, VDD3 Low Low Func.
GPIO15 by PMCF.
IO
CACHE_ZZ. Level 2 cache sleep mode output. This is designed to be Output, VDD3 Low Low Func.
connected to the power-control input to the second level cache to place it IO
into low-power mode. It is controlled by C3A50. This pin may also be
configured as GPIO8 by PMC8.
CPUSLEEP#. Processor non-snoop sleep mode output. This may be Output, VDD3 High High Func.
connected to the sleep pin of the processor to place it into a non-snoop-
IO
capable low-power state. It is controlled by C3A50. This pin may also be
configured as GPIO5 by PMC5.
CPUSTOP#. Processor clock stop output. This may be connected to the Output, VDD3 High High Func.
system clock chip to control the host clock signals. It is controlled by
IO
C3A50. This pin may also be configured as GPIO6 by PMC6.
DCSTOP#. DRAM controller stop output. This may be connected to the Output, VDD_ Active High Func.
system memory controller to indicate that its clock is going to stop (so that IO AUX
an alternative DRAM refresh scheme may start). It is controlled by
C3A50. This signal is also functional during STD, STR and SOFF.
EXTSMI#. External SMI input. This pin may be used to generate SMI Input, VDD_ - - -
or SCI interrupts and resume events. This pin may also be configured as IO AUX
GPIO12 by PMCC.
FLAGRD#. Flag read output. This may be connected to the output-
Output, VDD3 High High High
enable input of external buffers with the buffer outputs on the SD pins.
IO
Therefore, the inputs to the buffers may be software-readable flags.
FLAGRD# is asserted during reads of PM1A. This pin may also be
configured as GPIO11 by PMCB.
FLAGWR. Flag write output. This may be connected to the latch-
Output, VDD3 Low Low Low
enabled input of external latches with the latch inputs on the SD pins.
IO
Therefore, the outputs of the latches may be software-controlled flags.
FLAGWR is asserted during writes to PM18. This pin may also be
configured as GPIO10 by PMCA.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AMD-766.PDF ] | |
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