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W982508AH 데이터시트 PDF




Winbond에서 제조한 전자 부품 W982508AH은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 W982508AH 기능
기능 8M X 4 BANKS X 8 BIT SDRAM
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W982508AH 데이터시트, 핀배열, 회로
www.DataSheet4U.com
W982508AH
GENERAL DESCRIPTION
8M × 4 BANKS × 8 BIT SDRAM
W982508AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
8M words × 4 banks × 8 bits. Using pipelined architecture and 0.175 µm process technology,
W982508AH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the
personal computer industrial standard, W982508AH is sorted into three speed grades: -7, -75 and -
8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the
PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W982508AH is ideal for main memory in
high performance applications.
FEATURES
3.3V ±0.3V Power Supply
Up to 143 MHz Clock Frequency
8,388,608 Words × 4 Banks × 8 Bits Organization
Auto Refresh and Self Refresh
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and Full Page
Burst Read, Single Writes Mode
Byte Data Controlled by DQM
Power-down Mode
Auto-precharge and Controlled Precharge
4K Refresh Cycles/64 mS
Interface: LVTTL
Packaged in TSOP II 54-pin, 400 mil - 0.80
KEY PARAMETERS
SYM.
DESCRIPTION
tCK Clock Cycle Time
tAC Access Time from CLK
tRP Precharge to Active Command
tRCD Active to Read/Write Command
ICC1 Operation Current (Single bank)
ICC4 Burst Operation Current
ICC6 Self-refresh Current
MIN.
/MAX.
Min.
Max.
Min.
Min.
Max.
Max.
Max.
-7
(PC133, CL2)
7 nS
5.4 nS
15 nS
15 nS
80 mA
100 mA
3 mA
-75
(PC133, CL3)
7.5 nS
5.4 nS
20 nS
20 nS
75 mA
95 mA
3 mA
-8H
(PC100)
8 nS
6 nS
20 nS
20 nS
70 mA
90 mA
3 mA
Publication Release Date: December 2000
- 1 - Revision A1




W982508AH pdf, 반도체, 판매, 대치품
BLOCK DIAGRAM
W982508AH
CLK
CKE
CLOCK
BUFFER
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10
A0
A9
A11
A12
BS0
BS1
ADDRESS
BUFFER
MODE
REGISTER
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
DATA CONTROL
CIRCUIT
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DQ
BUFFER
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
DQ0
DQ7
DQM
Note: The cell array configuration is 8192 * 1024 * 8.
-4-

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W982508AH 전자부품, 판매, 대치품
W982508AH
DC CHARACTERISTICS
(VCC = 3.3V ± 0.3V, TA = 0°70°C)
PARAMETER
Operating Current
tCK = min., tRC = min.
Active precharge command
cycling without burst
operation
Standby Current
1 bank
operation
CKE = VIH
tCK = min, CS = VIH
VIH/L = VIH (min.)/VIL (max.)
Bank: Inactive state
Standby Current
CKE = VIL
(Power
Down mode)
CKE = VIH
CLK = VIL, CS = VIH
VIH/L = VIH (min.)/VIL (max.)
BANK: Inactive state
CKE = VIL
(Power down
mode)
No Operating Current
CKE = VIH
tCK = min., CS = VIH (min.)
BANK: Active state
(4 banks)
CKE = VIL
(Power down
mode)
Burst Operating Current
tCK = min.
Read/ Write command cycling
Auto Refresh Current
tCK = min.
Auto refresh command cycling
Self Refresh Current
Self Refresh Mode
CKE = 0.2V
SYM.
ICC1
ICC2
ICC2P
ICC2S
ICC2PS
ICC3
ICC3P
ICC4
ICC5
ICC6
-7
(PC133, CL2)
MIN. MAX.
80
40
1
10
1
60
10
100
170
3
-75
(PC133, CL3)
MIN. MAX.
75
35
1
10
1
55
10
95
160
3
-8H
(PC100)
MIN. MAX.
70
UNIT NOTES
3
30 3
13
10
1 mA
50
10
90 3, 4
150 3
3
PARAMETER
Input Leakage Current
(0V VIN VCC, all other pins not under test = 0V)
Output Leakage Current
(Output disable, 0V VOUT VCCQ)
LVTTL Output HLevel Voltage
(IOUT = -2 mA)
LVTTL Output LLevel Voltage
(IOUT = 2 mA)
SYMBOL
II(L)
IO(L)
VOH
VOL
MIN.
-5
-5
2.4
-
MAX.
5
5
-
0.4
UNIT
µA
µA
V
V
NOTES
Publication Release Date: December 2000
- 7 - Revision A1

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W982508AH

8M X 4 BANKS X 8 BIT SDRAM

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