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PDF CS5460 Data sheet ( Hoja de datos )
| Número de pieza | CS5460 | |
| Descripción | Single Phase Bi-directional Power/energy ic | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS5460
Single Phase Bi-Directional Power/Energy IC
Features
l Energy Data Linearity: 0.1% of Reading over
1000:1 Dynamic Range
l On-Chip Functions: Energy, I ∗ V,
IRMS and VRMS, Energy to Pulse-Rate
Conversion
l Complies with IEC 687/1036, JIS
l Power Consumption <12 mW
l Interface Optimized for Shunt Sensor
l Phase Compensation
l Ground-Referenced Signals with Single
Supply
l System Calibration
l On-chip 2.5 V Reference (60 ppm/°C drift)
l Simple Three-wire Serial Interface
l Watch Dog Timer
l Power Supply Monitor
l Power Supply Configurations
- VA+ = +5 V; VA- = 0V; VD+ = +3 V to +5 V
- VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V
Description
The CS5460 is a highly integrated ∆Σ Analog-to-Digital
Converter (ADC) which combines two ∆Σ ADCs, high
speed power calculation functions, and a serial interface
on a single chip. It is designed to accurately measure
and calculate: Energy, Instantaneous Power, IRMS, and
VRMS for single phase 2 or 3-wire power meter applica-
tions. The CS5460 interfaces to a low cost shunt or
transformer to measure current, and resistive divider or
transformer to measure voltage. The CS5460 features a
bi-directional serial interface for communication with a
micro-controller and a fixed-width programmable fre-
quency output that is proportional to energy. The product
is initialized and fully functional upon power-up, and in-
cludes facilities for system-level calibration under control
of the user program.
ORDERING INFORMATION:
CS5460-BS -40°C to +85°C
24-pin SSOP
VA+
RESET
VD+
IIN+ PGA
IIN- x10,x50
4th Order
∆Σ
Modulator
VIN+
VIN-
VREFIN
VREFOUT
x10 2nd Order
∆Σ
Modulator
x1
Voltage
Reference
Power
Monitor
Digital
Filter
Digital
Filter
System
Clock
/K
High Pass
Filter
Power
Calculation
Engine
(Energy
I*V
IRMS ,VRMS )
High Pass
Filter
Clock
Generator
Watch Dog
Timer
Serial
Interface
E-to-F
Calibration
SRAM
CS
SDI
SDO
SCLK
INT
EDIR
EOUT
VA- PFMON
XIN XOUT CPUCLK
DGND
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2000
(All Rights Reserved)
JUL ‘00
DS279PP6
1
1 page  
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CS5460
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol Min Typ Max Unit
Dynamic Characteristics
Phase Compensation
(Voltage Channel at 60 Hz)
-2.4
-
+2.5
°
High Rate Filter Output Word Rate
(Both Channels) OWR
- DCLK/1024 -
Hz
High Pass Filter Pole Frequency
-3 dB
- 0.5 - Hz
Reference Output
Output Voltage
REFOUT 2.4 - 2.6 V
Temperature Coefficient
- 25 60 ppm/°C
Load Regulation (Output Current 1 µA Source or Sink) ∆VR
-
6 10 mV
Output Noise Voltage
(0.1 Hz to 512 kHz) eN
-
100
- µVrms
Reference Input
Input Voltage Range
VREFIN 2.4 2.5 2.6 V
Input Capacitance
- 4 - pF
Input CVF Current
- 25 - nA
Power Supplies
Power Supply Currents (Normal Mode)
IA+ PSCA
-
1.3
- mA
ID+ (VD+ = 5 V) PSCD
-
2.9
- mA
ID+ (VD+ = 3 V) PSCD
-
1.7
- mA
Power Consumption
(Note 6)
Normal Mode (VD+ = 5 V) PC
-
21 25 mW
Normal Mode (VD+ = 3 V)
- 11.6 - mW
Standby
- 6.75 - mW
Sleep
- 10 - µW
Power Supply Rejection
(50, 60 Hz)
(Gain = 10)
(Gain = 50)
PSRR
PSRR
56
70
-
-
dB
dB
Power Monitor Thresholds
PM 2.3
2.7 V
Notes: 6. All outputs unloaded. All inputs CMOS level.
5 V DIGITAL CHARACTERISTICS (TA = -40 °C to +85 °C; VA+, VD+ = 5 V ±10% VA-, DGND = 0
V) (See Notes 2 and 7)
Parameter
Symbol
Min
Typ Max Unit
High-Level Input Voltage All Pins Except XIN and SCLK VIH
0.6 VD+
-
-
V
XIN (VD+) - 0.5 - - V
SCLK
0.8 VD+
-
-
V
Low-Level Input Voltage
All Pins Except XIN and SCLK VIL
-
- 0.8 V
XIN - - 1.5
SCLK
- - 0.2 VD+
High-Level Output Voltage
Iout = +5 mA VOH (VD+) - 1.0
-
-
V
Low-Level Output Voltage
Iout = -5 mA VOL
-
- 0.4 V
Input Leakage Current
Iin - ±1 ±10 µA
3-State Leakage Current
IOZ - - ±10 µA
Digital Output Pin Capacitance
Cout
-
5 - pF
DS279PP6
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5 Page 
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CS5460
VOLTAGE ∆Σ
DELAY
REG
SINC 2
DELAY
REG
FIR
Configuration Register *
PC[3:0] Bits
HPF
APF
CURRENT ∆Σ
SINC 4
FIR HPF
APF
V off * V gn *
V*
+x
x SINC2
N
V RMS*
x
+x
N
Σ
P*
x SINC2
TBC *
x ÷ 4096
E*
E to F
E out
E dir
PULSE-RATE*
N I RMS *
I off * I gn *
I*
* DENOTES REGISTER NAME
Figure 5. Data Flow.
2.2.1 Single Computation Cycle (C = 0)
Based on the information provided in the Cycle
Count register, a single computation cycle is per-
formed after the user transmits the single conver-
sion cycle command. After the computations are
complete, DRDY is set. Thirty-two SCLKs are
then needed to acquire a calculation result. The first
8 SCLKs are used to clock in the command to de-
termine which result register is to be read. The last
24 SCLKs are needed to read the desired calcula-
tion result register. After reading the data, the serial
port returns to the command mode, where it waits
for a new command to be issued.
2.2.2 Multiple Computation Cycles (C = 1)
Based on the information provided in the Cycle
Count register, continuous computation cycles are
repeatedly performed on the voltage and current
cycles. Computation cycles cannot be start-
ed/stopped on a per channel basis. After each com-
putation cycle is completed, DRDY is set.
Thirty-two SCLKs are then needed to read a regis-
ter. The first 8 SCLKs are used to clock in the com-
mand to determine which results register is to be
read. The last 24 SCLKs are needed to read the cal-
culation result. While in this mode, the user may
choose to acquire only the calculations required for
the application as DRDY rises and falls to indicate
the availability of a new data.
The RMS calculations require a Sinc2 operation
prior to their square root operation. Therefore, the
first output for each channel will be invalid (i.e. all
RMS calculations are invalid in the single compu-
tation cycle routine and the first RMS calculations
will be invalid in the continuous computation cy-
cle). All energy calculations will be valid since en-
ergy calculations don’t require this Sinc2 operation.
2.3 High Rate Digital Filters
The high rate filter on the voltage channel is imple-
mented as a fixed sinc2 filter, compensated by a
short length FIR. When the converter is driven with
a 4.096 MHz clock (K=1), the filter has a magni-
tude response similar to that shown in Figure 6.
Note that the filter’s response scales with MCLK
frequency and K.
The current channel contains a sinc4 filter, compen-
sated by a short length FIR. When the converter is
driven with a 4.096 MHz clock (K=1) the compos-
ite filter response is given in Figure 7.
DS279PP6
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5460.PDF ] | |
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