PDF AN1406 Data sheet ( Hoja de datos )

Número de pieza	AN1406
Descripción	DESIGNING
Fabricantes	ON Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de AN1406 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas
No Preview Available ! www.DataSheet4U.com AN1406/D Designing with PECL (ECL at +5.0 V) The High Speed Solution for the CMOS/TTL Designer Prepared by Cleon Petty Todd Pearson ECL Applications Engineering http://onsemi.com APPLICATION NOTE This application note provides detailed information on designing with Positive Emitter Coupled Logic (PECL) devices. Introduction PECL, or Positive Emitter Coupled Logic, is nothing more than standard ECL devices run off of a positive power supply. Because ECL, and therefore PECL, has long been the “black magic” of the logic world many misconceptions and falsehoods have arisen concerning its use. However, many system problems which are difficult to address with TTL or CMOS technologies are ideally suited to the strengths of ECL. By breaking through the wall of misinformation concerning the use of ECL, the TTL and CMOS designers can arm themselves with a powerful weapon to attack the most difficult of high speed problems. It has long been accepted that ECL devices provide the ultimate in logic speed; it is equally well known that the price for this speed is a greater need for attention to detail in the design and layout of the system PC boards. Because this requirement stems only from the speed performance aspect of ECL devices, as the speed performance of any logic technology increases these same requirements will hold. As can be seen in Table 1 the current state–of–the–art TTL and CMOS logic families have attained performance levels which require controlled impedance interconnect for even relatively short distances between source and load. As a result system designers who are using state–of–the–art TTL or CMOS logic are already forced to deal with the special requirements of high speed logic; thus it is a relatively small step to extend their thinking from a TTL and CMOS bias to include ECL devices where their special characteristics will simplify the design task. Table 1. Relative Logic Speeds Logic Family 10KH Typical Output Rise/Fall 1.0ns Maximum Open Line Length (Lmax)* 3″ ECLinPS 400ps 1″ FAST 2.0ns 6″ FACT 1.5ns 4″ * Approximate for stripline interconnect (Lmax = Tr/2Tpd) System Advantages of ECL The most obvious area to incorporate ECL into an otherwise CMOS/TTL design would be for a subsystem which requires very fast data or signal processing. Although this is the most obvious it may also be the least common. Because of the need for translation between ECL and CMOS/TTL technologies the performance gain must be greater than the overhead required to translate back and forth between technologies. With typical delays of six to seven nanoseconds for translating between technologies, a significant portion of the logic would need to be realized using ECL for the overall system performance to improve. However, for very high speed subsystem requirements ECL may very well provide the best system solution. Transmission Line Driving Many of the inherent features of an ECL device make it ideal for driving long, controlled impedance lines. The low impedance of the open emitter outputs and high input impedance of any standard ECL device make it ideally suited for driving controlled impedance lines. Although designed to drive 50Ω lines an ECL device is equally adept at driving lines of impedances of up to 130Ω without significant changes in the AC characteristics of the device. Although some of the newer CMOS/TTL families have the ability to drive 50Ω lines many require special driver circuits to supply the necessary currents to drive low impedance transmission interconnect. In addition the large output swings and relatively fast output slew rates of today’s high performance CMOS/TTL devices exacerbate the problems of crosstalk and EMI radiation. The problems of crosstalk and EMI radiation, along with common mode noise and signal amplitude losses, can be alleviated to a great degree with the use of differential interconnect. Because of their architectures, neither CMOS nor TTL devices are capable of differential communication. The differential amplifier input structure and complimentary outputs of ECL devices make them perfectly suited for differential applications. As a result, for systems requiring signal transmission between © Semiconductor Components Industries, LLC, 1999 September, 1999 – Rev. 2 1 Publication Order Number: AN1406/D 1 page AN1406/D Parallel Termination Schemes Because the techniques using an extra VTT power supply consume significantly less power, as the number of PECL devices incorporated in the design increases the more attractive the VTT supply termination scheme becomes. Typically ECL is specified driving 50Ω into a –2.0V, therefore for PECL with a VCC supply different than ground the VTT terminating voltage will be VCC – 2.0V. Ideally the VTT supply would track 1:1 with VCC, however in theory this scenario is highly unlikely. To ensure proper operation of a PECL device within the system the tolerances of the VTT and the VCC supplies should be considered. Assume for instance that the nominal case is for a 50Ω load (Rt) into a +3.0V supply; for a 10H compatible device with a VOHmax of –0.81V and a realistic VOLmin of –1 .85V the following can be derived: IOHmax = (VOHmax – VTT)/Rt IOHmax = ({5.0 – 0.81} – 3.0)/50 = 23.8mA IOLmin = (VOLmin – VTT)/Rt IOLmin = ({5.0 – 1.85} – 3.0)/50 = 3.0mA If +5% supplies are assumed a VCC of VCCnom –5% and a VTT of VTTnom +5% will represent the worst case. Under these conditions, the following output currents will result: IOHmax = ({4.75 – 0.81} – 3.15)/50 = 15.8mA IOLmin = ({4.75 – 1.85} – 3.15)/50 = 0mA Using the other extremes for the supply voltages yields: IOHmax = 31.8mA IOLmin = 11mA The changes in the IOH currents will affect the DC VOH levels by ≈±40mV at the two extremes. However in the vast majority of cases the DC levels for ECL devices are well centered in their specification windows, thus this variation will simply move the level within the valid specification window and no loss of worst case noise margin will be seen. The IOL situation on the other hand does pose a potential AC problem. In the worst case situation the output emitter follower could move into the cutoff state. The output emitter followers of ECL devices are designed to be in the conducting “on” state at all times. If cutoff, the delay of the device will be increased due to the extra time required to pull the output emitter follower out of the cutoff state. Again this situation will arise only under a number of simultaneous worst case situations and therefore is highly unlikely to occur, but because of the potential it should not be overlooked. Thevenin Equivalent Termination Schemes The Thevenin equivalent parallel termination technique of Figure 3 is likely the most attractive scheme for the CMOS/TTL designer who is using a small amount of ECL. As mentioned earlier this technique will consume more power, however the absence of an additional power supply will more than compensate for the extra power consumption. In addition, this extra power is consumed entirely in the external resistors and thus will not affect the reliability of the IC. As is the case with standard parallel termination, the tolerances of the VTT and VCC supplies should be addressed in the design phase. The following equations provide a means of determining the two resistor values and the resulting equivalent VTT terminating voltage. R1 = R2 ({VCC – VTT}/{VTT – VEE}) R2 = ZO ({VCC – VEE}/{VCC – VTT}) VTT = VCC (R2/{R1 + R2}) For the typical setup: VCC = 5.0V; VEE = GND; VTT = 3.0V; and ZO = 50Ω R2 = 50 ({5 – 0}/{5–3}) = 125Ω R1 = 125 ({5–3}/{3–0}) = 83.3Ω checking for VTT VTT = 5 (125/{125 – 83.3}) = 3.0V ZO Rpd VEE Open Line Termination Rs ZO Rpd VEE RS = ZO Series Termination ZO Rt = ZO Rt VTT Parallel Termination VCC ZO R1 R2 VEE Thevenin Parallel Termination Figure 3. Termination Techniques for ECL/PECL Devices Because of the resistor divider network used to generate VTT the variation in V will be intimately tied to the variation in VCC. Differentiating the equation for VTT with respect to VCC yields: dVTT/dVCC = R2/(R1 + R2) dVCC http://onsemi.com 5 5 Page

Páginas	Total 8 Páginas
PDF Descargar	[ Datasheet AN1406.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AN1406	DESIGNING	ON Semiconductor
AN1406D	DESIGNING	ON Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar