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VRS51C1100 데이터시트 PDF




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기능 Versa 8051 MCU
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VRS51C1100 데이터시트, 핀배열, 회로
www.DataSheet4U.com
VRS51C1100
Datasheet
Rev 1.1
Versa 8051 MCU with 128KB of IAP/ISP Flash
Overview
The VRS51C1100 is based on the standard 8051
microcontroller architecture and is a pin compatible
drop-in replacement for the 8051.
The VRS51C1100 is aimed at a diversity of applications
that require a large amount of program/data memory
with non-volatile data storage and/or code/field based
firmware upgrade capability coupled with
comprehensive peripheral support. It features 64KB of
In-System/In-Application Programmable Flash memory,
64KB Data Flash memory, 1KB of RAM, 4 PWM
outputs, a UART, three 16-bit timers/counters, a
watchdog timer and power down features.
The VRS51C1000 is available with firmware that
enables In-System Programming (firmware based boot-
loader) of the Flash memory via the UART interface
(ISPVx version). General Flash memory programming
is supported by device programmers available from
Ramtron or other 3rd party commercial programmer
suppliers.
The VRS51C1100 is available in PLCC-44, QFP-44
and DIP-40 packages and functions over the industrial
temperature range.
FIGURE 1: VRS51C1100 FUNCTIONAL DIAGRAM
64KB
Data FLASH
64KB
Program
FLASH
1024 Bytes of
RAM
8051
PROCESSOR
ADDRESS/
DATA BUS
PORT 0
PORT 1
8
8
UART
PORT 2
8
2 INTERRUPT
INPUTS
TIMER 0
TIMER 1
TIMER 2
RESET
POWER
CONTROL
WATCHDOG
TIMER
PORT 3
PORT 4
PWM
8
4
4
Feature Set
80C51/80C52 pin compatible
64KB Program + 64KB Data Flash memory
In-System / In-Application Flash Programming (ISP/IAP)
Program voltage: 5V
1024 Bytes on chip data RAM
Four 8-bit I/Os + one 4-bit I/O
4 PWM outputs on P1.3 to P1.7
One Full Duplex UART serial port
Three 16-bit Timers/Counters
Watchdog Timer
Bit operation instruction
8-bit Unsigned Multiply and Division instructions
BCD arithmetic
Direct and Indirect Addressing
Two Levels of Interrupt Priority and Nested Interrupts
Power saving modes
Code protection function
Low EMI (inhibit ALE)
Operating Temperature Range -40ºC to +85ºC
FIGURE 2: VRS51C1100 QFP-44 AND PLCC-44 PIN OUT DIAGRAMS
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P4.2
T2/P1.0
T2EX/P1.1
PWM0/P1.2
PWM1/P1.3
PWM2/P1.4
33
34
23
22
VRS51C1100
QFP-44
44
1
12
11
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
P4.0
VSS
XTAL1
XTAL2
#RD/P3.7
#WR/P3.6
PWM3/P1.5
P1.6
P1.7
RES
RXD/P3.0
P4.3
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
6
7
17
18
40
39
VRS51C1000
PLCC-44
29
28
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#EA
P4.1
ALE
#PSEN
P2.7/A15
P2.6/A14
P2.5/A13
Ramtron International Corporation ? http://www.ramtron.com
1850 Ramtron Drive Colorado Springs ? MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208
Colorado, USA, 80921 ? 1-800-545-FRAM, 1-719-481-7000
page 1 of 50




VRS51C1100 pdf, 반도체, 판매, 대치품
VRS51C1100
Instruction Set
Mnemonic
Description
Size
(bytes)
The following table describes the VRS51C1100 instruction
set. The instructions are function and binary code
compatible with industry standard 8051s.
TABLE 3: LEGEND FOR INSTRUCTION SET TABLE
Symbol
A
Rn
Direct
@Ri
rel
bit
#data
#data 16
addr 16
addr 11
Function
Accumulator
Register R0-R7
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two's complement offset byte
Direct bit address
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
TABLE 4: VRS51C1100 INSTRUCTION SET
Mnemonic
Description
Arithmetic instructions
ADD A, Rn
Add register to A
ADD A, direct
Add direct byte to A
ADD A, @Ri
Add data memory to A
ADD A, #data
Add immediate to A
ADDC A, Rn
Add register to A with carry
ADDC A, direct
Add direct byte to A with carry
ADDC A, @Ri
Add data memory to A with carry
ADDC A, #data
Add immediate to A with carry
SUBB A, Rn
Subtract register from A with borrow
SUBB A, direct
Subtract direct byte from A with borrow
SUBB A, @Ri
Subtract data mem from A with borrow
SUBB A, #data
Subtract immediate from A with borrow
INC A
Increment A
INC Rn
Increment register
INC direct
Increment direct byte
INC @Ri
Increment data memory
DEC A
Decrement A
DEC Rn
Decrement register
DEC direct
Decrement direct byte
DEC @Ri
Decrement data memory
INC DPTR
Increment data pointer
MUL AB
Multiply A by B
DIV AB
Divide A by B
DA A
Decimal adjust A
Logical Instructions
ANL A, Rn
AND register to A
ANL A, direct
AND direct byte to A
ANL A, @Ri
AND data memory to A
ANL A, #data
AND immediate to A
ANL direct, A
AND A to direct byte
ANL direct, #data AND immediate data to direct byte
ORL A, Rn
OR register to A
ORL A, direct
OR direct byte to A
ORL A, @Ri
OR data memory to A
ORL A, #data
OR immediate to A
ORL direct, A
OR A to direct byte
ORL direct, #data OR immediate data to direct byte
XRL A, Rn
Exclusive-OR register to A
XRL A, direct
Exclusive-OR direct byte to A
XRL A, @Ri
Exclusive-OR data memory to A
XRL A, #data
Exclusive-OR immediate to A
XRL direct, A
Exclusive-OR A to direct byte
XRL direct, #data Exclusive-OR immediate to direct byte
CLR A
Clear A
CPL A
Compliment A
SWAP A
Swap nibbles of A
RL A
Rotate A left
RLC A
Rotate A left through carry
RR A
Rotate A right
RRC A
Rotate A right through carry
Size
(bytes)
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
Instr. Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
Boolean Instruction
CLR C
Clear Carry bit
CLR bit
Clear bit
SETB C
Set Carry bit to 1
SETB bit
Set bit to 1
CPL C
Complement Carry bit
CPL bit
Complement bit
ANL C,bit
Logical AND between Carry and bit
ANL C,#bit
Logical AND between Carry and not bit
ORL C,bit
Logical ORL between Carry and bit
ORL C,#bit
Logical ORL between Carry and not bit
MOV C,bit
Copy bit value into Carry
MOV bit,C
Copy Carry value into Bit
Data Transfer Instructions
MOV A, Rn
Move register to A
MOV A, direct
Move direct byte to A
MOV A, @Ri
Move data memory to A
MOV A, #data
Move immediate to A
MOV Rn, A
Move A to register
MOV Rn, direct
Move direct byte to register
MOV Rn, #data
Move immediate to register
MOV direct, A
Move A to direct byte
MOV direct, Rn
Move register to direct byte
MOV direct, direct Move direct byte to direct byte
MOV direct, @Ri
Move data memory to direct byte
MOV direct, #data Move immediate to direct byte
MOV @Ri, A
Move A to data memory
MOV @Ri, direct
Move direct byte to data memory
MOV @Ri, #data
Move immediate to data memory
MOV DPTR, #data Move immediate to data pointer
MOVC A, @A+DPTR
Move code byte relative DPTR to A
MOVC A, @A+PC Move code byte relative PC to A
MOVX A, @Ri
Move external data (A8) to A
MOVX A, @DPTR Move external data (A16) to A
MOVX @Ri, A
Move A to external data (A8)
MOVX @DPTR, A Move A to external data (A16)
PUSH direct
Push direct byte onto stack
POP direct
Pop direct byte from stack
XCH A, Rn
Exchange A and register
XCH A, direct
Exchange A and direct byte
XCH A, @Ri
Exchange A and data memory
XCHD A, @Ri
Exchange A and data memory nibble
Branching Instructions
ACALL addr 11
Absolute call to subroutine
LCALL addr 16
Long call to subroutine
RET
Return from subroutine
RETI
Return from interrupt
AJMP addr 11
Absolute jump unconditional
LJMP addr 16
Long jump unconditional
SJMP rel
Short jump (relative address)
JC rel
Jump on carry = 1
JNC rel
Jump on carry = 0
JB bit, rel
Jump on direct bit = 1
JNB bit, rel
Jump on direct bit = 0
JBC bit, rel
Jump on direct bit = 1 and clear
JMP @A+DPTR
Jump indirect relative DPTR
JZ rel
Jump on accumulator = 0
JNZ rel
Jump on accumulator 1= 0
CJNE A, direct, rel
Compare A, direct JNE relative
CJNE A, #d, rel
Compare A, immediate JNE relative
CJNE Rn, #d, rel
Compare reg, immediate JNE relative
CJNE @Ri, #d, rel Compare ind, immediate JNE relative
DJNZ Rn, rel
Decrement register, JNZ relative
DJNZ direct, rel
Decrement direct byte, JNZ relative
Miscellaneous Instruction
NOP
No operation
Rn: Any of the register R0 to R7
@Ri: Indirect addressing using Register R0 or R1
#data: immediate Data provided with Instruction
#data16: Immediate data included with instruction
bit: address at the bit level
rel: relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d: Immediate Data supplied with instruction
1
2
1
2
1
2
2
2
2
2
2
2
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
2
3
1
1
2
3
2
2
2
3
3
3
1
2
2
3
3
3
3
2
3
1
Instr. Cycles
1
1
1
1
1
1
2
2
2
2
1
2
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
_______________________________________________________________________________________________
www.ramtron.com
page 4 of 50

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VRS51C1100 전자부품, 판매, 대치품
VRS51C1100
An alternate way to force the VRS51C1100 to jump to
the ISP boot program is to maintain pins P2.6 and P2.7
or pin P4.3 at a low logic level during a hardware reset,
as shown in the diagram below:
FIGURE 4: VRS51C1100 ALTERNATE ISP BOOT PROGRAM ACCESS
10ms
10ms
P2.7
P2.6
RES
OR...
P4.3
RES
10ms
10ms
The ISP boot program can also be accessed via the
LJMP instruction.
When the ISP page configuration is set to 0 while the
device is being programmed with a parallel
programmer, the ISP boot feature will be disabled.
VRS51C1100 ISPVx Firmware Boot Program
An ISP boot loader program is available for the
VRS51C1100. (ISPVx Firmware, x = revision, see
Ramtron website for latest revision) that resides in
locations F200h to FFFFh in the upper 3.5KB of the
VRS51C1100 Program Flash memory. The ISPVx
Firmware enables In-System-Programming of the
VRS51C1100 on the final application PCB using the
UART interface.
The VRS51C1100 can be ordered with or without the
ISPVx bootloader firmware (see the ordering
information section of this datasheet for part number
information).
See the following figure for a hardware configuration
example. Other configurations are also possible.
FIGURE 5: VRS51C1100 INTERFACE FOR IN-SYSTEM PROGRAMMING
To PC
VRS51C1100
(with ISPV2
Firmware)
TXD
RXD
Creset
PNP
150k
RES
Rreset
Visit the Ramtron web site to download the “Versa
Ware ISP” Window™’s application, which enables
communication with the ISPVx firmware.
The ISPVx bootloader firmware can also be
programmed into the VRS51C1000 by the user.
Source code is included with the Versa Ware ISP
application software.
For more information on the ISPVx firmware, please
consult the “VRS51C1100 ISPVx Firmware User
Guide.pdf,” available on the Ramtron web site.
Note: The current ISPVx firmware and Versa Ware
software does not allow VRS51C1100 Data Flash
programming. Future versions of both will provide
support for VRS51C1100 Data Flash programming.
______________________________________________________________________________________________
www.ramtron.com
page 7 of 50

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