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PDF ADM3088 Data sheet ( Hoja de datos )
| Número de pieza | ADM3088 | |
| Descripción | (ADM3082 -ADM3089) Transceivers | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADM3088 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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PRELIMINARY TECHNICAL DATA
High-Speed(10Mbps),Fail-Safe,RS-485/RS-422
a
TransceiverswithSlew-Rate-Limiting
and±15kVESD Protection
ADM3082/ADM3085/ADM3088
FEATURES
Enhanced Slew Rate Limiting for Error-Free Data
Transmission
Fail-Safe Receiver Operation while Maintaining
EIA/TIA-485 compatibility
Low-Current (1nA) Shutdown Mode
High Input Impedance — Up to 256 Transceivers on Bus
±15kV ESD Protection (Human Body Model) on
RS-485 I/O pins
Pin-Compatible with Industry Standard 75176
APPLICATIONS
Enhanced Replacement for Industry-Standard Parts
EMI-Sensitive Systems
Level Translation
LANs for Industrial Control Applications
GENERAL DESCRIPTION
The ADM3082/ADM3085/ADM3088 are high-speed
RS-485/RS-422 transceivers consisting of one driver and one
receiver per package. The devices feature fail-safe operation,
ensuring a logic-high receiver output when the receiver in-
puts are open-circuit or short-circuit. This guarantees that
the receiver output will be high if all the transmitters on a
terminated bus are disabled (high-impedance).
The ADM3082 has a slew-rate limited driver to minimize
electromagnetic interference (EMI) and reduce reflections
caused by incorrectly terminated cables. This allows error-
free transmission at data rates up to 115kbps.
The ADM3085 offers a higher slew rate allowing data rates
up to 500kbps, while the ADM3088 has a driver whose slew
rate is not limited, allowing data rates up to 10Mbps.
All devices in the family feature ±15kV electrostatic dis-
charge (ESD) protection and high receiver input imped-
ance (1/8 unit load), allowing up to 256 transceivers on
the bus. The devices have low current drain of 375µA un-
loaded, or fully loaded with the drivers disabled, and fea-
ture an ultra-low power (1nA) shutdown mode.
FUNCTIONAL BLOCK DIAGRAM
RO 1
RE 2
DE 3
DI 4
R
D
8 VCC
7B
6A
5 GND
ADM3082/ADM3085/ADM 3088
REV. PrA 02/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 2002
1 page  
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PRELIMINARY TECHNICAL DATA
ADM3082/ADM3085/ADM3088
ADM3082/ADM3085/ADM3088 SPECIFICATIONS (continued)
SWITCHINGCHARACTERISTICS—ADM3085
(VCC = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.) (Note 1)
Parameter
Min Typ Max Units Test Conditions/Comments
Driver Input-to-Output, tDPLH
Driver Input-to-Output, tDPHL
Driver Output Skew,|tDPLH - tDPHL|, tDSKEW
250
250
Driver Rise or Fall Time, tDR, tDF
200
Maximum Data Rate, fMAX
Driver Enable to Output High, tDZH
500
720 1000 ns Figures 2 and 3 RDIFF = 54⍀,
720 1000 ns CL1 = CL2 = 100pF
–3
±100
ns Figures 2 and 3, RDIFF = 54⍀,
CL1 = CL2 = 100pF
530 750 ns Figures 2 and 3, RDIFF = 54⍀,
CL1 = CL2 = 100pF
kbps
2500
ns Figures 5 and 6, CL = 100pF,
S2 closed
Driver Enable to Output Low, tDZL
2500
ns Figures 5 and 6, CL = 100pF,
S1 closed
Driver Disable Time from Low, tDLZ
100 ns Figures 5 and 6, CL = l5pF,
S1 closed
Driver Disable Time from High, tDHZ
100 ns Figures 5 and 6, CL = l5pF,
S2 closed
Receiver Input to Output, tRPLH, tRPHL
Differential Receiver Skew, tRSKD
|tRPLH - tRPHL|
Receiver Enable to Output Low, tRZL
127 200 ns Figure 7; |VID| Ն 2.0V;
rise and fall time of VID Յ l5ns
3 ±30 ns Figure 7; |VID| Ն 2.0V;
rise and fall time of VID Յ l5ns
20 50 ns Figures 7 and 8 CL = 100pF,
S1 closed
Receiver Enable to Output High, tRZH
20 50 ns Figures 7 and 8, CL = 100pF,
S2 closed
Receiver Disable Time from Low, tRLZ
20 50 ns Figures 7 and 8, CL = 100pF,
S1 closed
Receiver Disable Time from High, tRHZ
20 50 ns Figures 7 and 8, CL = 100pF,
S2 closed
Time to Shutdown, tSHDN
Driver Enable from Shutdown
to Output High, tDZH(SHDN)
Driver Enable from Shutdown
to Output Low, tOZL(SHDN)
Receiver Enable from Shutdown
to Output High, tRZH(SHDN)
Receiver Enable from Shutdown
to Output Low, tRZL(SHDN)
50 200 600 ns (Note 5)
4500
ns Figures 5 and 6, CL = l5pF,
S2 closed
4500
ns Figures 5 and 6, CL = l5pF,
S1 closed
3500
ns Figures 7 and 8, CL = 100pF,
S2 closed
3500
ns Figures 7 and 8, CL = 100pF,
S1 closed
REV. PrA 02/02
–5–
5 Page 
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PRELIMINARY TECHNICAL DATA
ADM3082/ADM3085/ADM3088
PIN FUNCTION DESCRIPTION
Pin Mnemonic
Description
1 RO
Receiver Output. When RE is low and A - B Ն (more positive than) –50mV, RO will be high.
When RE is low and A – B Յ (more negative than) –200mV, RO will be low.
2 RE
Receiver Output Enable. Take RE low to enable RO; RO is high impedance when RE is high.
Take RE high and DE low to enter low-power shutdown mode.
3 DE
Driver Output Enable. Take DE high to enable driver outputs. These outputs are high
impedance when DE is low. Take RE high and DE low to enter low-power shutdown mode.
4 DI
Driver Input. With DE high, a low on DI forces non-inverting output low and inverting output
high. Similarly, a high on DI forces non-inverting output high and inverting output low.
5 GND
Ground
6A
Non-Inverting Receiver Input and Non-Inverting Driver Output
7B
Inverting Receiver Input and Inverting Driver Output
8 VCC
Positive Supply 4.75V =VCC =5.25V
TRANSMITTING
INPUTS
R E DE
X1
X1
00
10
DI
1
0
X
X
DEVICE TRUTH TABLES
OUTPUTS
RECEIVING
B/Z A/Y
RE
01
0
10
0
High-Z
High-Z
0
Shutdown
1
1
INPUTS
DE
X
X
X
1
0
A-B
Ն -0.05V
Յ -0.2V
Open/shorted
X
X
OUTPUT
RO
1
0
1
High-Z
Shutdown
X = Don’t care
Shutdown mode, driver and receiver outputs high impedance
REV. PrA 02/02
–11–
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ADM3088.PDF ] | |
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