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부품번호 ADM3071E 기능
기능 (ADM3070E - ADM3078E) low power data transceivers
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ADM3071E 데이터시트, 핀배열, 회로
www.DataSheet4U.com
3.3 V, ±15 kV ESD-Protected, Half- and
Full-Duplex, RS-485/RS-422 Transceivers
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
FEATURES
TIA/EIA RS-485/RS-422 compliant
±15 kV ESD protection on RS-485 input/output pins
Data rates
ADM3070E/ADM3071E/ADM3072E: 250 kbps
ADM3073E/ADM3074E/ADM3075E: 500 kbps
ADM3076E/ADM3077E/ADM3078E: 16 Mbps
Half- and full-duplex options
True fail-safe receiver inputs
Up to 256 nodes on the bus
−40°C to +125°C temperature option
Hot-swap input structure on DE and RE pins
Reduced slew rates for low EMI
Low power shutdown current (all except
ADM3071E/ADM3074E/ADM3077E)
Outputs high-Z when disabled or powered off
Common-mode input range: −7 V to +12 V
Thermal shutdown and short-circuit protection
8-lead and 14-lead narrow SOIC packages
APPLICATIONS
Power/energy metering
Industrial control
Lighting systems
Telecommunications
Security systems
Instrumentation
GENERAL DESCRIPTION
The ADM3070E to ADM3078E are 3.3 V, low power data
transceivers with ±15 kV ESD protection suitable for full- and
half-duplex communication on multipoint bus transmission
lines. They are designed for balanced data transmission, and they
comply with TIA/EIA standards RS-485 and RS-422.
The devices have an ⅛ unit load receiver input impedance,
which allows up to 256 transceivers on a bus. Because only one
driver should be enabled at any time, the output of a disabled or
powered-down driver is tristated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which
eliminates the need for external bias resistors and ensures a
logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
before communication begins and when communication ceases.
FUNCTIONAL BLOCK DIAGRAMS
VCC
ADM3070E/
ADM3073E/
ADM3076E
RO R
RE
DE
DI D
A
B
Z
Y
GND
Figure 1.
VCC
ADM3071E/
ADM3074E/
ADM3077E
A
RO R B
DI D
Z
Y
GND
Figure 2.
VCC
ADM3072E/
ADM3075E/
ADM3078E
.
RO R
RE
DE
DI D
A
B
GND
Figure 3.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
(continued on Page 3)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.




ADM3071E pdf, 반도체, 판매, 대치품
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ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
SPECIFICATIONS
VCC = 3.3 V ± 10%, TA = TMIN to TMAX, unless otherwise noted.
Table 2. ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
Parameter
Symbol Min
Typ Max Unit Test Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage
VOD
Δ|VOD| for Complementary Output States1
Common-Mode Output Voltage
Δ|VOC| for Complementary Output States1
Short-Circuit Output Current
ΔVOD
VOC
ΔVOC
IOSD
2.0
1.5
40
VCC V
RL = 100 Ω (RS-422) (see Figure 7)
VCC V
RL = 54 Ω (RS-485) (see Figure 7)
VCC V
No load
0.2 V
R = 54 Ω or 100 Ω (see Figure 7)
VCC/2 3 V R = 54 Ω or 100 Ω (see Figure 7)
0.2 V
R = 54 Ω or 100 Ω (see Figure 7)
250 mA 0 V < VOUT < 12 V
250
40 mA 7 V < VOUT < VCC
Short-Circuit Foldback Output Current IOSDF 20
mA (VCC 1 V) < VOUT < 12 V
Output Leakage (Y, Z) Full Duplex
IO
20 mA 7 V < VOUT < +1 V
125 μA DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = 12 V
100
μA DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V
Logic Inputs
Input High Voltage
VIH 2.0
V DE, DI, RE
Input Low Voltage
VIL
0.8 V
DE, DI, RE
Input Hysteresis
VHYS 100 mV DE, DI, RE
Logic Input Current
IIN1
±1 μA DE, DI, RE
Input Impedance First Transition
1 10 kΩ DE
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TTS
TTSH
175 °C
15 °C
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Input Hysteresis
Input Resistance (A, B)
Input Current (A, B)
VTH
ΔVTH
RIN
IA, B
200
96
100
125 50
15
125
mV
mV
μA
μA
7 V < VCM < +12 V
VA + VB = 0 V
7 V < VCM < +12 V
DE = 0 V, VCC = 0 V or 3.6 V, VIN = 12 V
DE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V
RO Logic Output
Output High Voltage
Output Low Voltage
Short-Circuit Output Current
Tristate Output Leakage Current
VOH VCC 0.6
VOL
IOSR
IOZR
V
0.4 V
±80 mA
±1 μA
IOUT = −1 mA
IOUT = 1 mA
0 V < VRO < VCC
VCC = 3.6 V, 0 V < VOUT < VCC
POWER SUPPLY
Supply Current
ICC 0.8 1.5 mA No load, DE = VCC, RE = 0 V
0.8 1.5 mA No load, DE = VCC, RE = VCC
0.8 1.5 mA No load, DE = 0 V, RE = 0 V
Shutdown Current
ISHDN 0.05 10 μA DE = 0 V, RE = VCC
ESD PROTECTION
A, B, Y, Z Pins
±15 kV Human body model
All Pins Except A, B, Y, Z Pins
±4 kV Human body model
1 Δ|VOD| and Δ|VOC| are the changes in VOD and VOC, respectively, when the DI input changes state.
Rev. A | Page 4 of 20

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ADM3071E 전자부품, 판매, 대치품
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ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
TIMING SPECIFICATIONS—ADM3076E/ADM3077E/ADM3078E
VCC = 3.3 V ± 10%, TA = TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter
Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate
Propagation Delay, Low to High Level
Propagation Delay, High to Low Level
Rise Time/Fall Time
|tDPLH − tDPHL| Differential Driver Output Skew
tDPLH
tDPHL
tDR/tDF
tDSKEW
16
Mbps
50 ns
CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
50 ns
CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
15 ns
CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
8 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
Enable to Output High
tDZH
150 ns
(See Figure 10)
Enable to Output Low
tDZL
150 ns
(See Figure 11)
Disable Time from Low
tDLZ
100 ns
(See Figure 11)
Disable Time from High
tDHZ
100 ns
(See Figure 10)
Enable Time from Shutdown to High
tDZH(SHDN)
1250 1800 ns
(See Figure 10)
Enable Time from Shutdown to Low
tDZL(SHDN)
1250 1800 ns
(See Figure 11)
RECEIVER
Maximum Data Rate
16 Mbps
Propagation Delay, Low to High Level
tRPLH
40 75 ns
CL = 15 pF (see Figure 12 and Figure 13)
Propagation Delay, High to Low Level
tRPHL
40 75 ns
CL = 15 pF (see Figure 12 and Figure 13)
|tRPLH − tRPHL| Output Skew
tRSKEW
8 ns CL = 15 pF (see Figure 12 and Figure 13)
Enable to Output High
tRZH
50 ns
(See Figure 14)
Enable to Output Low
tRZL
50 ns
(See Figure 14)
Disable Time from Low
tRLZ
50 ns
(See Figure 14)
Disable Time from High
tRHZ
50 ns
(See Figure 14)
Enable Time from Shutdown to High
tRZH(SHDN)
1800 ns
(See Figure 14)
Enable Time from Shutdown to Low
tRZL(SHDN)
1800 ns
(See Figure 14)
TIME TO SHUTDOWN
tSHDN
50 200 600 ns
Rev. A | Page 7 of 20

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부품번호상세설명 및 기능제조사
ADM3071E

(ADM3070E - ADM3078E) low power data transceivers

Analog Devices
Analog Devices

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