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부품번호 | 74AUP1G32 기능 |
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기능 | Low-power 2-input OR gate | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 16 페이지수
www.DataSheet4U.com
74AUP1G32
Low-power 2-input OR gate
Rev. 01 — 2 August 2005
Product data sheet
1. General description
The 74AUP1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G32 provides the single 2-input OR function.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-C exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C
Philips Semiconductors
74AUP1G32
Low-power 2-input OR gate
8. Functional description
8.1 Function table
Table 5:
Input
A
L
L
H
H
Function table [1]
B
L
H
L
H
[1] H = HIGH voltage level;
L = LOW voltage level.
9. Limiting values
Output
Y
L
H
H
H
Table 6: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK input clamping
current
VI < 0 V
−0.5 +4.6 V
- −50 mA
VI input voltage
IOK
output clamping
VO > VCC or VO < 0 V
current
[1] −0.5
-
+4.6
±50
V
mA
VO output voltage active mode
Power-down mode
[1] −0.5
[1] −0.5
VCC + 0.5 V
+4.6 V
IO
output current
VO = 0 V to VCC
- ±20 mA
ICC quiescent supply
current
- +50 mA
IGND
Tstg
Ptot
ground current
storage temperature
total power
dissipation
Tamb = −40 °C to +125 °C
-
−65
[2] -
−50
+150
250
mA
°C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9397 750 14678
Product data sheet
Rev. 01 — 2 August 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
4 of 16
4페이지 Philips Semiconductors
74AUP1G32
Low-power 2-input OR gate
Table 8: Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Typ
ICC quiescent supply current VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current
VCC = 3.3 V
Tamb = −40 °C to +125 °C
VIH HIGH-state input voltage VCC = 0.8 V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VIL LOW-state input voltage VCC = 0.8 V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VOH HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VOL LOW-state output voltage VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
ILI input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
∆IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC quiescent supply current VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
∆ICC
quiescent additional supply VI = VCC − 0.6 V; IO = 0 A;
current
VCC = 3.3 V
-
[1] -
-
-
0.75 × VCC -
0.70 × VCC -
1.6 -
2.0 -
--
--
--
--
VCC − 0.11 -
0.6 × VCC -
0.93 -
1.17 -
1.77 -
1.67 -
2.40 -
2.30 -
--
--
--
--
--
--
--
--
--
--
--
--
[1] -
-
[1] One input at VCC − 0.6 V, other input at VCC or GND.
Max Unit
0.9 µA
50 µA
-V
-V
-V
-V
0.25 × VCC V
0.30 × VCC V
0.7 V
0.9 V
-V
-V
-V
-V
-V
-V
-V
-V
0.11 V
0.33 × VCC V
0.41 V
0.39 V
0.36 V
0.50 V
0.36 V
0.50 V
±0.75
µA
±0.75
µA
±0.75
µA
1.4 µA
75 µA
9397 750 14678
Product data sheet
Rev. 01 — 2 August 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
7 of 16
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부품번호 | 상세설명 및 기능 | 제조사 |
74AUP1G32 | Low-power 2-input OR gate | NXP Semiconductors |
74AUP1G32 | SINGLE 2 INPUT POSITIVE OR GATE | Diodes |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |