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부품번호 ADF4108 기능
기능 PLL Frequency Synthesizer
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ADF4108 데이터시트, 핀배열, 회로
Data Sheet
PLL Frequency Synthesizer
ADF4108
FEATURES
GENERAL DESCRIPTION
8.0 GHz bandwidth
3.2 V to 3.6 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3.3 V systems
Programmable, dual-modulus prescaler
8/9, 16/17, 32/33, or 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
Loop filter design possible with ADIsimPLL
4 mm × 4 mm, 20-lead chip scale package
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio
The ADF4108 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion sections
of wireless receivers and transmitters. It consists of a low noise
digital PFD (phase frequency detector), a precision charge pump, a
programmable reference divider, programmable A and B counters,
and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B
(13-bit) counters, in conjunction with the dual-modulus prescaler
(P/P + 1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R counter), allows selectable REFIN
frequencies at the PFD input. A complete phase-locked loop (PLL)
can be implemented if the synthesizer is used with an external
loop filter and voltage controlled oscillator (VCO). Its very high
bandwidth means that frequency doublers can be eliminated in
many high frequency systems, simplifying system architecture
and reducing cost.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT INPUT
REGISTER
22
FUNCTION
LATCH
SDOUT
FROM
FUNCTION
LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
6-BIT
A COUNTER
CE AGND DGND
6
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
HIGH-Z
19 AVDD
MUX
MUXOUT
SDOUT
M3 M2 M1
ADF4108
Figure 1.
Rev. E
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADF4108 pdf, 반도체, 판매, 대치품
Data Sheet
ADF4108
SPECIFICATIONS
AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to
TMAX, unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency3
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity4
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency6
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOH, Output High Voltage
IOH, Output High Current
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD (AIDD + DIDD)7
IP
Power-Down Mode (AIDD + DIDD)8
B Version1
1.0/8.0
−5/+5
300
325
20/250
0.8/VDD
10
±100
104
5
625
2.5
3.0/11
1
2
1.5
2
1.4
0.6
±1
10
1.4
VDD − 0.4
100
0.4
3.2/3.6
AVDD
AVDD/5.5
17
0.4
10
B Chips2
(Typ)
Unit
1.0/8.0
−5/+5
300
325
GHz min/max
dBm min/max
MHz max
MHz max
20/250
0.8/VDD
10
±100
MHz min/max
V p-p min/max
pF max
µA max
104 MHz max
5
625
2.5
3.0/11
1
2
1.5
2
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
1.4 V min
0.6 V max
±1 µA max
10 pF max
1.4
VDD − 0.4
100
0.4
V min
V min
µA max
V max
3.2/3.6
AVDD
AVDD/5.5
17
0.4
10
V min/max
V min/max
mA max
mA max
µA typ
Test Conditions/Comments
See Figure 11 for input circuit
For lower frequencies, ensure slew rate (SR) > 320 V/µs
P=8
P = 16
For f < 20 MHz, ensure SR > 50 V/µs
Biased at AVDD/25
Programmable; see Figure 18
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
See Figure 18
1 nA typical; TA = 25°C
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V
CMOS output chosen
IOL = 500 µA
AVDD ≤ VP ≤ 5.5 V
15 mA typ
TA = 25°C
Rev. E | Page 3 of 20

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ADF4108 전자부품, 판매, 대치품
ADF4108
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to GND1
AVDD to DVDD
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
RFINA to RFINB
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
CSP θJA Thermal Impedance
(Paddle Soldered)
Reflow Soldering
Peak Temperature (60 sec)
Time at Peak Temperature
Transistor Count
CMOS
Bipolar
Rating
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to VDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
±600 mV
−40°C to +85°C
−65°C to +125°C
150°C
30.4°C/W
260°C
40 sec
6425
303
1 GND = AGND = DGND = 0 V.
Data Sheet
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
Rev. E | Page 6 of 20

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