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Número de pieza | PDU1016H | |
Descripción | ECL-INTERFACED PROGRAMMABLE DELAY LINE | |
Fabricantes | Data Delay Devices | |
Logotipo | ||
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4-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU1016H)
PDU1016H
data
delay
3
®
devices, inc.
FEATURES
• Digitally programmable in 16 delay steps
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully 10KH-ECL interfaced & buffered
• Fits 32-pin DIP socket
PACKAGES
GND
ENB
1 32 GND
2 31 OUT
A0
VEE
GND
7 26 A1
8 25 A2
9 24 GND
IN 11
N/C
N/C
OUT
GND
ENB
N/C
N/C
N/C
GND
ENB
N/C
IN
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
N/C
A2
A1
VEE
A0
N/C
N/C
N/C
VEE
A3
N/C
N/C
PDU1016H-xxC4 SMD
PDU1016H-xxMC4 Mil SMD
A3
VEE
15
16
PDU1016H-xx DIP
PDU1016H-xxM Mil DIP
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU1016H-series device is a 4-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on
the address code (A3-A0) according to the following formula:
IN Signal Input
OUT Signal Output
A0-A3 Address Bits
ENB Output Enable
TDA = TD0 + TINC * A
VEE -5 Volts
GND Ground
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the
device and can range from 0.5ns through 100ns, inclusively. The enable pin (ENB) is held LOW during
normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not
latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 1ns,
whichever is greater
• Inherent delay (TD0): 5.5ns typical for dash numbers
up to 5, greater for larger #’s
• Setup time and propagation delay:
Address to input setup (TAIS): 3.6ns
Disable to output delay (TDISO): 1.7ns typical
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VEE: -5VDC ± 5%
• Power Dissipation: 615mw typical (no load)
• Minimum pulse width: 20% of total delay
NOTE: Any dash number between .5 and 100
not shown is also available.
©2001 Data Delay Devices
DASH NUMBER SPECIFICATIONS
Part
Number
PDU1016H-.5
PDU1016H-1
PDU1016H-2
PDU1016H-3
PDU1016H-4
PDU1016H-5
PDU1016H-6
PDU1016H-8
PDU1016H-10
PDU1016H-15
PDU1016H-20
PDU1016H-25
PDU1016H-30
PDU1016H-40
PDU1016H-50
PDU1016H-60
PDU1016H-80
PDU1016H-100
Incremental Delay
Per Step (ns)
0.5 ± 0.3
1.0 ± 0.5
2.0 ± 0.5
3.0 ± 1.0
4.0 ± 1.0
5.0 ± 1.0
6.0 ± 1.0
8.0 ± 1.0
10.0 ± 1.5
15.0 ± 1.5
20.0 ± 2.0
25.0 ± 2.5
30.0 ± 3.0
40.0 ± 4.0
50.0 ± 5.0
60.0 ± 6.0
80.0 ± 8.0
100.0 ± 10.0
Total
Delay (ns)
7.5 ± 1.0
15 ± 1.0
30 ± 1.5
45 ± 2.2
60 ± 3.0
75 ± 3.7
90 ± 4.5
120 ± 6.0
150 ± 7.5
225 ± 11.2
300 ± 15.0
375 ± 18.8
450 ± 22.5
600 ± 30.0
750 ± 37.5
900 ± 45.0
1200 ± 60.0
1500 ± 75.0
Doc #97044
11/1/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1 page PDU1016H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): -5.0V ± 0.1V
Input Pulse:
Standard 10KH ECL
levels
Source Impedance: 50Ω Max.
Rise/Fall Time:
2.0 ns Max. (measured
between 20% and 80%)
Pulse Width:
PWIN = 1.5 x Total Delay
Period:
PERIN = 10 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
50Ω to -2V
5pf ± 10%
(VOH + VOL) / 2
(Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PULSE
GENERATOR
OUT
TRIG
IN DEVICE UNDER OUT
TEST (DUT)
REF
IN
TRIG
OSCILLOSCOPE
ADDRESS SELECT
Test Setup
INPUT
SIGNAL
OUTPUT
SIGNAL
TRISE
PWIN
PERIN
TFALL
80% VIH 80%
50%
50%
20%
20%
VIL
DRISE
DFALL
50%
VOH
50%
Timing Diagram For Testing
VOL
Doc #97044
11/1/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
5 Page |
Páginas | Total 5 Páginas | |
PDF Descargar | [ Datasheet PDU1016H.PDF ] |
Número de pieza | Descripción | Fabricantes |
PDU1016H | ECL-INTERFACED PROGRAMMABLE DELAY LINE | Data Delay Devices |
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