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ADV7342 데이터시트 PDF




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부품번호 ADV7342 기능
기능 (ADV7342 / ADV7343) Multiformat Video Encoder
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ADV7342 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
74.25 MHz 16-/24-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
Six 11-bit, 297 MHz video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD), 4:4:4 YCrCb (ED and HD), and
4:4:4 RGB (SD, ED, and HD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Simultaneous SD and ED/HD operation
EIA/CEA-861B compliance support
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
On-board voltage reference (optional external input)
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (FSC) and phase
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Undershoot limiter
Dual data rate (DDR) input support
Multiformat Video Encoder
Six, 11-Bit, 297 MHz DACs
ADV7342/ADV7343
Enhanced definition(ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7342 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7342 only)
Copy generation management system (CGMS)
Wide screen signaling
Closed captioning
Serial MPU interface with I2C compatibility
3.3 V analog operation, 1.8 V digital operation, and 1.8 V or
3.3 V I/O operation
Temperature range: −40°C to +85°C
Qualified for automotive applications
APPLICATIONS
DVD recorders and players
High definition Blu-ray DVD players
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADV7342 pdf, 반도체, 판매, 대치품
ADV7342/ADV7343
REVISION HISTORY
7/15—Rev. D to Rev. E
Changes to Features Section............................................................ 1
Changes to Ordering Guide ........................................................ 106
Added Automotive Products Section......................................... 106
3/12—Rev. C to Rev. D
Changed ADV7340/ADV7341 to ADV7342/ADV7343........... 70
3/12—Rev. B to Rev. C
Reorganized Layout............................................................Universal
Change to Features Section ............................................................. 1
Moved Revision History Section .................................................... 4
Change to Table 1 ............................................................................. 5
Changes to Digital Input/Output Specifications—
1.8 V Section ..................................................................................... 8
Changes to Table 15........................................................................ 21
Changes to Table 21........................................................................ 33
Changes to Table 24........................................................................ 36
Changes to Table 29........................................................................ 41
Changes to Table 30........................................................................ 42
Changes to 24-Bit 4:4:4 RGB Mode Section ............................... 48
Deleted ED/HD Nonstandard Timing Mode Section, Figure 59,
and Table 42, Renumbered Sequentially ..................................... 50
Deleted Subaddress 0x84, Bits[2:1] Section, Timing Reset (TR)
Mode Section, Subcarrier Phase Reset (SCR) Mode Section, and
Figure 60 .......................................................................................... 51
Deleted Figure 61............................................................................ 52
Added External Sync Polarity Section ......................................... 52
Changed SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section to SD Subcarrier Frequency
Lock Section .................................................................................... 53
Changes to ED/HD Test Patterns Section ................................... 81
9/11—Rev. A to Rev. B
Changes to MPU Port Description Section ................................ 27
3/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Deleted Detailed Features Section, Changes to Table 1............... 4
Changes to Figure 1.......................................................................... 5
Changes to Table 6............................................................................ 7
Added Digital Input/Output Specifications—1.8 V Section and
Table 7 ................................................................................................ 7
Changes to Digital Timing Specifications—3.3 V Section and
Table 8 ................................................................................................ 8
Added Table 9.................................................................................... 9
Changes to MPU Port Timing Specifications Section,
Default Conditions ......................................................................... 10
Data Sheet
Deleted Figure 20............................................................................ 18
Changes to Table 13 ....................................................................... 19
Changes to Table 15 ....................................................................... 20
Changes to MPU Port Description Section ................................ 27
Changes to I2C Operation Section ............................................... 27
Added Table 16 ............................................................................... 27
Added Figure 49 ............................................................................. 28
Changes to Table 17 ....................................................................... 29
Changes to Table 18 ....................................................................... 29
Changes to Table 21, 0x30 Bit Description ................................. 32
Changes to Table 29 ....................................................................... 39
Changes to Table 30 ....................................................................... 40
Changes to Table 31, 0xA0 Register Name ................................. 42
Changes to Table 32 ....................................................................... 43
Added Table 33 and Table 34 ........................................................ 44
Changes to Standard Definition Only Section ........................... 46
Added Figure 52 ............................................................................. 47
Changes to Figure 53...................................................................... 47
Changes to Figure 56, Figure 57, and Figure 58 ......................... 48
Renamed Features Section to Design Features Section............. 50
Changes to ED/HD Nonstandard Timing Mode Section......... 50
Changes to Figure 60...................................................................... 51
Added HD Interlace External P_HSYNC and P_VSYNC
Considerations Section.................................................................. 51
Changes to SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section .................................................. 51
Changes to Programming the FSC Section................................... 53
Changes to Subaddress 0x8C to Subaddress 0x8F Section ....... 53
Changes to Subaddress 0x82, Bit 4 Section................................. 53
Added SD Manual CSC Matrix Adjust Feature Section............ 56
Changes to Subaddress 0x9C to Subaddress 0x9F Section ....... 57
Changes to SD Brightness Detect Section................................... 58
Changes to Figure 71...................................................................... 60
Added Sleep Mode Section ........................................................... 68
Changes to Pixel and Control Port Readback Section .............. 68
Added SD Teletext Insertion Section........................................... 68
Added Unused Pins Section.......................................................... 70
Added Figure 86 and Figure 87 .................................................... 70
Changes to Power Supply Sequencing Section........................... 72
Changes to Figure 94...................................................................... 75
Changes to SD Wide Screen Signaling Section .......................... 77
Changes to Internal Test Pattern Generation Section ............... 79
Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option
(Subaddress 0x8A = XXXXX000) Section.................................. 80
Added Configuration Scripts Section.......................................... 92
10/06—Revision 0: Initial Version
Rev. E | Page 4 of 106

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ADV7342 전자부품, 판매, 대치품
Data Sheet
SPECIFICATIONS
POWER SUPPLY AND VOLTAGE SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 2.
Parameter
SUPPLY VOLTAGES
VDD
VDD_IO
PVDD
VAA
POWER SUPPLY REJECTION RATIO
Min
1.71
1.71
1.71
2.6
Typ
1.8
3.3
1.8
3.3
0.002
VOLTAGE REFERENCE SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 3.
Parameter
Internal Reference Range, VREF
External Reference Range, VREF
External VREF Current1
1 External current required to overdrive internal VREF.
Min
1.186
1.15
Typ
1.248
1.235
±10
INPUT CLOCK SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 4.
Parameter
fCLKIN_A
fCLKIN_A
fCLKIN_A
fCLKIN_B
fCLKIN_B
CLKIN_A High Time, t9
CLKIN_A Low Time, t10
CLKIN_B High Time, t9
CLKIN_B Low Time, t10
CLKIN_A Peak-to-Peak Jitter Tolerance
CLKIN_B Peak-to-Peak Jitter Tolerance
Conditions1
SD/ED
ED (at 54 MHz)
HD
ED
HD
Min Typ
27
54
74.25
27
74.25
40
40
40
40
2
2
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
ADV7342/ADV7343
Max
1.89
3.63
1.89
3.465
Unit
V
V
V
V
%/%
Max Unit
1.31 V
1.31 V
µA
Max Unit
MHz
MHz
MHz
MHz
MHz
% of one clock cycle
% of one clock cycle
% of one clock cycle
% of one clock cycle
±ns
±ns
Rev. E | Page 7 of 106

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