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PDF PONE-000-01 Data sheet ( Hoja de datos )
| Número de pieza | PONE-000-01 | |
| Descripción | The ideal device | |
| Fabricantes | Domosys | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PONE-000-01 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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CEWay™ is a family of chips
developed by DOMOSYS Corporation to meet
the requirements of the residential and
commercial local area networks (LANs). The
CEWay PL-One is the ideal device for simple
nodes, such as switches, actuators and
sensors. It integrates the complete Physical
Layer of the CEBus® standard (EIA-600) and
an M8052 core microcontroller. It provides you
with all of the resources you need to embed
the upper layers of the CEBus standard and
the user application into a single-chip solution.
The CEWay PL-One is designed for superior
performance in noisy power line environments.
Features
• CEBus power line Physical Layer
• Power line medium dependent
Physical and Symbol Encoding
Sublayers
• Proprietary DSP for superior signal
Reception in noisy environments
• M8052 core microcontroller
• 4 SFRs for communication between
PLSES and M8052
P1.4 P1.3 P0.1 P1.2 P0.0 P1.1 VDD P1.0 VSSRESET* P3.7 AGND RSVD VREFRSVD CEBin AVCC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
P1.5 10
VDD 11
P0.2 12
P0.3 13
P0.4
14
P0.5 15
P0.6 16
P0.7 17
RSVD 18
P2.0 19
P2.1 20
P2.2 21
P2.3 22
P2.4 23
P2.5 24
VSS 25
P1.6 26
Domosys Corp.
CEWayTM
PL - One
CW00I0A
703123
60 VSS
59 CEBout
58 RSVD
57 RSVD
56 PSEN*
55 ALE
54 RSVD
53 VDD
52 SELCLK
51 VSS
50 RSVD
49 RSVD
48 RSVD
47 RSVD
46 RSVD
45 CEBAM
44 TEST
27 28
29 30 31
32 33 34
35
36 37 38 39 40 41 42 43
P1.7 VDD P2.6 VDD P2.7 XTAL2 XTAL1 RSVD VSS P3.3 RSVD P3.0 P3.6 P3.4 RSVD P3.1 P3.5
Figure 1 Pin-out for CEWay PL-One
• Up to 64 KB of external data memory
• 256 bytes of internal data memory
• Up to 64 KB of external code memory
(can be extended with bank switching)
• Three 16-bit timer/counters
• Full-duplex serial port
• 15 I/O pins
• 68-pin PLCC package
• Industrial operating temperature range
D-CW-0100-04
Page 1 of 56
1 page  
March 2000
CEWay™ PL-One Data Sheet
Electrical Specifications
Absolute Maximum Rating1
Parameter
Sym Min
Max Units Test Conditions
Supply Voltage
VDD- Vss -0.3
7
V
DC Input Voltage
VIN -0.3 VDD +0.3 V
DC Input Current
Storage Temperature
IIN
TS T G
-10
-40
+10
+125
mA
OC
ESD Tolerance
2 kV
1 Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
DC Electrical Characteristics - Voltages are with respect to VSS unless otherwise stated
Parameter
Sym
Min Typ2-3 Max Units Test Conditions
Supply Voltage - Digital
VDD
4.75
5
5.25 V
Supply Voltage - Analog
AVCC 4.75 5 5.25 V
Input Voltage (high)
VIH 0.7VDD
VDD+0.3 V
Input Voltage (low)
VIL VSS-0.3
0.3VDD V
Output Voltage (high)
VOH 2.4
V IOH = 50 µA
Output Voltage (low)
VOL
0.4 V
IOL = 4 mA
Operating Current Digital
IVDD
25 35 mA fCLK = 14.318 MHz
Operating Current Analog
IAVCC
9.5 15.5 mA fCLK = 14.318 MHz
Operating Temperature
TO -40
+85 OC
2 Typical figures are at 25 OC and are for design aid only: not guaranteed and not subject to production testing.
3 DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
AC Electrical Characteristics
Parameter
Sym
Min Typ4 Max Units
CEBout Output Voltage
CEBout Load Impedance
VCEBout
ZLCEBout
5
3.5
V p-p
kΩ
CEBin Input Impedance
Clock Frequency5
ZinCEBin
40
68 140 kΩ
fCLK 14.31818
21.4772 MHz
Pin Capacitance XTAL1,XTAL2 CXTAL 0.8 pF
Input Pin Capacitance
CI
8 pF
Output Pin Capacitance
Co
8 pF
4 Typical figures are at 25 OC and are for design aid only: not guaranteed and not subject to production testing.
5 Clock frequency can only be either 14.31818 or 21.4772 MHz for proper chirp timing.
Test Conditions
fCLK = 14.318 MHz
fCLK = 14.318 MHz
D-CW-0100-04
Page 5 of 56
5 Page 
March 2000
Bit
rx_del1
rx_del0
jabber (LSB)
CEWay™ PL-One Data Sheet
Bits in Ph_Confirm_Reg
Description
D e s c r i p t i o n : R e c e p t i o n d e l i m i t e r s . In RCV state, this pair of
bits indicates the type of delimiter which terminates the current byte. Their
configuration is shown below in Table 4.
HW Reset state: 00
Enable trigger:
• Set to 11 when a PEOF symbol has been detected and received.
• Set to 10 when an EOP symbol has been detected and received. Also set
to 10 after the CRC has been received and the checksum result is
available, or set to 10 when the reception timestamp bytes are being
passed to the PL-One firmware.
• Set to 01 when an EOF symbol has been detected and received.
• Set to 00 when 8 consecutive packet Data symbols have been saved in
Ph_Rx_Buffer before receiving an EOF or EOP delimiter symbol. This
case can happen for any packet field part, including those transmitted with
Leading Zero Suppression (LZS). Also set to 00 when a PEOF symbol
has been received but fewer than 8 Preamble symbols were detected.
This situation is likely to happen with a Medium Noisy indication (see
ch_noisy bit).
Reset trigger: It is reset when the PLSES Handshake Interrupt is reset.
D e s c r i p t i o n : J a b b e r D e t e c t . In XMIT state, it indicates that the
PL-One has transmitted at least 1,000 consecutive SUPERIOR symbols. In
RCV state, it indicates that the PL-One has received at least 1,000
consecutive SUPERIOR symbols.
HW Reset state: 0
Enable trigger: Set to 1 after the PL-One has transmitted at least 1,000
consecutive SUPERIOR symbols. Also set to 1 after the PL-One has
received at least 1,000 consecutive SUPERIOR symbols.
Reset trigger: It is reset when 1024 consecutive SUPERIOR states have
been detected on the channel in either transmission or reception.
Table 3 Explanation of Bits in Ph_Confirm_Reg SFR
Symbol
EOF
EOP
PEOF
No delimiter
del1 del0
01
10
11
00
# USTs
3
4
8
0
Table 4 Bit Representation of Four Possible Delimiters (EOF, EOP, PEOF, and none)
D-CW-0100-04
Page 11 of 56
11 Page | ||
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| PDF Descargar | [ Datasheet PONE-000-01.PDF ] | |
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