S75NS128N Datasheet PDF - SPANSION
| Part Number | S75NS128N | |
| Description | Burst-mode Multiplexed Flash | |
| Manufacturers | SPANSION | |
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S75NS-N
S29NS-N: MirrorBit™ 1.8 Volt-only Simultaneous Read/
Write, Burst-mode Multiplexed Flash (NOR Interface)
S30MS-P: ORNAND™ Flash (NAND interface)
Multiplexed Synchronous pSRAM
Data Sheet (Advance Information)
S75NS-N Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S75NS-N_00
Revision 01E
Issue Date May 3, 2006
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Data Sheet (Advance Information)
2. Input/Output Descriptions
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
AMAX – A16
ADQ15 – ADQ0
OE#
WE#
VSS
F-RDY / R-WAIT
CLK
AVD#
F-RST#
F-WP#
F-ACC
F-CE#
VCC
R-CE1#
R-CRE
R-VCC
R-UB#
R-LB#
N-CLE
N-ALE
N-CE#
N-WE#
N-RE#
N-IO0 - N-IO7
N-WP#
N-RY/BY#
N-PRE
N-VSS
N-VCC
DNU
NC
Signal
Type
Input
I/O
Input
Input
Ground
Output
Input
Input
Input
Input
Input
Input
Power
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
I/O
Input
Input
Input
Ground
Power
—
—
Description
Address inputs
Multiplexed Address/Data
Output Enable input. Asynchronous relative to CLK for the Burst
mode.
Write Enable input.
Ground
Ready output. Indicates the status of the Burst read. The WAIT#
pin of the pSRAM is tied to RDY.
Clock input. In burst mode, after the initial word is output,
subsequent active edges of CLK increment the internal address
counter. Should be at VIL or VIH while in asynchronous mode
Address Valid input. Indicates to device that the valid address is
present on the address inputs. Low = for asynchronous mode,
indicates valid address; for burst mode, causes starting address
to be latched. High = device ignores address inputs
Hardware reset input. Low = device resets and returns to reading
array data
Hardware write protect input. At VIL, disables program and erase
functions in the four outermost sectors. Should be at VIH for all
other conditions.
Accelerated input. At VHH, accelerates programming;
automatically places device in unlock bypass mode. At VIL,
disables all program and erase functions. Should be at VIH for all
other conditions.
Chip-enable input for Flash. Asynchronous relative to CLK for
Burst Mode.
Flash 1.8 Volt-only single power supply
Chip-enable input for pSRAM
Control Register Enable (pSRAM)
pSRAM Power Supply
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Command Latch Enable
Address Latch Enable
Chip Enable input for ORNAND
Write Enable input
Read Enable input
Data Input/Output
Hardware write protect input. At VIL, disables program and erase
functions in the four outermost sectors. Should be at VIH for all
other conditions.
Ready/Busy output
Power-On Read Enable
Ground
ORNAND 1.8 Volt-only single power supply.
Do Not Use
No Connect; not connected internally
NS
(NOR)
X
X
X
X
X
X
X
X
X
X
X
X
X
pSRAM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MS
(ORNAND)
X
X
X
X
X
X
X
X
X
X
X
S75NS-N_00_01E May 3, 2006
S75NS-N
3
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for S75NS128N electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ S75NS128N.PDF Datasheet ] | |
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