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30SPA0553 데이터시트 PDF




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부품번호 30SPA0553 기능
기능 GaAs MMIC Power Amplifier
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30SPA0553 데이터시트, 핀배열, 회로
www.DataSheet4U.com
27.0-32.0 GHz GaAs MMIC
Power Amplifier
September 2005 - Rev 01-Sep-05
Features
Ka-Band 2W Power Amplifier
22.0 dB Small Signal Gain
+33.0 dBm Saturated Output Power
+40.0 dBm Output Third Order Intercept (OIP3)
100% On-Wafer RF, DC and Output Power Testing
100% Visual Inspection to MIL-STD-883
Method 2010
30SPA0553
Chip Device Layout
General Description
Mimix Broadband's three stage 27.0-32.0 GHz GaAs
MMIC power amplifier has a small signal gain of 22.0
dB with +33 dBm saturated output power.This MMIC
uses Mimix Broadbands 0.15 µm GaAs PHEMT device
model technology, and is based upon electron beam
lithography to ensure high repeatability and
uniformity.The chip has surface passivation to protect
and provide a rugged part with backside via holes
and gold metallization to allow either a conductive
epoxy or eutectic solder die attach process.This
device is well suited for Millimeter-wave Point-to-
Point Radio, LMDS, SATCOM and VSAT applications.
Absolute Maximum Ratings
Supply Voltage (Vd)
Supply Current (Id1,2,3)
Gate Bias Voltage (Vg)
Input Power (Pin)
Storage Temperature (Tstg)
Operating Temperature (Ta)
Channel Temperature (Tch)
+6.5 VDC
165,415,790 mA
+0.3 VDC
TBD
-65 to +165 OC
-55 to MTTF Table1
MTTF Table1
(1) Channel temperature affects a device's MTTF. It is
recommended to keep channel temperature as low as
possible for maximum life.
Electrical Characteristics (Ambient Temperature T = 25 oC)
Parameter
Frequency Range (f )
Input Return Loss (S11)
Output Return Loss (S22)
Small Signal Gain (S21)
Gain Flatness (ΔS21)
Reverse Isolation (S12)
Saturated Output Power (Psat)
Drain Bias Voltage (Vd1,2,3)
Gate Bias Voltage (Vg1,2,3)
Supply Current (Id1) (Vd=5.0V, Vg=-0.7V Typical)
Supply Current (Id2) (Vd=5.0V, Vg=-0.7V Typical)
Supply Current (Id3) (Vd=5.0V, Vg=-0.7V Typical)
Units Min. Typ. Max.
GHz 27.0 - 32.0
dB - 10.0 -
dB - 15.0 -
dB - 22.0 -
dB - +/-1.0 -
dB - 50.0 -
dBm - +33.0 -
VDC - +5.0 +6.0
VDC -1.2 -0.9 0.0
mA - 100 150
mA - 250 350
mA - 550 750
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com
Page 1 of 5
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Characteristic Data and
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tUo.Sc.hGaonvgeernwmitehnotu. Itnnpoutircceh.a©si2n0g05thMesime pixaBrtrso, aUd.Sb.aDnodm, Inesct.ic
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30SPA0553 pdf, 반도체, 판매, 대치품
27.0-32.0 GHz GaAs MMIC
Power Amplifier
September 2005 - Rev 01-Sep-05
30SPA0553
App Note [1] Biasing - It is recommended to separately bias each amplifier stage Vd1 through Vd3 at Vd(1,2,3)=5.0V with Id1=100mA, Id2=250mA,
and Id3=550mA. Separate biasing is recommended if the amplifier is to be used at high levels of saturation, where gate rectification will alter the
effective gate control voltage. For non-critical applications it is possible to parallel all stages and adjust the common gate voltage for a total drain
current Id(total)=1040 mA. It is also recommended to use active biasing to keep the currents constant as the RF power and temperature vary; this
gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the bias circuit may be a
single transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used to sense the current.The gate of
the pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate voltage needed to do this is -0.7V.Typically the
gate is protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure negative gate bias is
available before applying the positive drain supply.
App Note [2] Bias Arrangement -
For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain or gate pad DC bypass
capacitors (~100-200 pF) can be combined. Additional DC bypass capacitance (~0.01 uF) is also recommended to all DC or combination (if gate or
drains are tied together) of DC bias pads. All DC pads have been tied together on chip and can be biased from either side.
For Individual Stage Bias (Recommended for saturated applications) -- Each DC pad (Vd1,2,3 and Vg1,2,3) needs to have DC bypass capacitance
(~100-200 pF) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also recommended. All DC pads have been tied
together on chip and can be biased from either side.
MTTF Table (TBD)
These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry.
Backplate
Temperature
55 deg Celsius
75 deg Celsius
95 deg Celsius
Channel
Temperature
deg Celsius
deg Celsius
deg Celsius
Rth
MTTF Hours
FITs
C/W E+ E+
C/W E+ E+
C/W E+ E+
Bias Conditions: Vd1=Vd2=Vd3=5.0V, Id1=100mA, Id2=250mA, Id3=550mA
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com
Page 4 of 5
Export
of
this
item
Characteristic Data and
may require appropriate
Specifications are subject
export licensing from the
tUo.Sc.hGaonvgeernwmitehnotu. Itnnpoutircceh.a©si2n0g05thMesime pixaBrtrso, aUd.Sb.aDnodm, Inesct.ic
customers
accept
their obligation to be compliant with U.S. Export Laws.

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