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부품번호 | PE4308 기능 |
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기능 | RF Digital Attenuator | ||
제조업체 | Peregrine Semiconductor | ||
로고 | |||
전체 11 페이지수
www.DataSheet4U.com
Product Description
The PE4308 is a high linearity, 5-bit RF Digital Step Attenuator
(DSA) covering 31 dB attenuation range in 1dB steps, and is
pin compatible with the PE430x series. This 75-ohm RF DSA
provides both parallel (latched or direct mode) and serial
CMOS control interface, operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4308 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.
The PE4308 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
RF Input
Switched Attenuator Array
RF Output
Product Specification
PE4308
75 Ω RF Digital Attenuator
5-bit, 31 dB, DC – 4.0 GHz
Features
• Attenuation: 1 dB steps to 31 dB
• Flexible parallel and serial programming
interfaces
• Latched or direct mode
• Unique power-up state selection
• Positive CMOS control logic
• High attenuation accuracy and linearity
over temperature and frequency
• Very low power consumption
• Single-supply operation
• 75 Ω impedance
• Pin compatible with PE430x series
• Packaged in a 20 Lead 4x4 mm QFN
Figure 2. Package Type
20 Lead 4x4 mm QFN
Parallel Control 5
Serial Control 3
Power-Up Control 2
Control Logic Interface
Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V
Parameter
Test Conditions
Frequency
Minimum
Operation Frequency
Insertion Loss2
DC ≤ 1.2 GHz
DC
-
Attenuation Accuracy
1 dB Compression3,4
Input IP31,2,4
Return Loss
Any Bit or Bit
Combination
Two-tone inputs up to
+18 dBm
DC ≤ 1.2 GHz
1 MHz ≤ 1.2 GHz
1 MHz ≤ 1.2 GHz
DC ≤ 1.2 GHz
-
30
-
10
Switching Speed
50% control to 0.5 dB
of final value
-
Notes: 1. Device Linearity will begin to degrade below 1 MHz
2. Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
4. Measured in a 50 Ω system.
Typical
1.4
-
34
52
13
-
Maximum
2000
1.95
±(0.2 + 4% of atten setting)
Not to Exceed +0.4 dB
-
-
-
1
Units
MHz
dB
dB
dB
dBm
dBm
dB
µs
Document No. 70-0162-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE4308
Product Specification
Typical Performance Data (25°C, VDD=3.0 V unless otherwise noted)
Figure 6. Insertion Loss (Zo=75 ohms)
Figure 7. Attenuation at Major steps
0
-1
-2
-3
-4
-5
0
500
1000
1500
2000
RF Frequency (MHz)
35
30
25
20
15
10
5
0
0
31dB
16dB
8dB
4dB
2dB
1dB
500
1000
1500
RF Frequency (MHz)
2000
Figure 8. Input Return Loss at Major
Attenuation Steps (Zo=75 ohms)
0
-10
-20
-30 8dB
16dB
31dB
-40
-50
0
500
1000
1500
RF Frequency (MHz)
2000
Figure 9. Output Return Loss at Major
Attenuation Steps (Zo=75 ohms)
0
-10
-20
-30
-40
-50
0
500
1000
1500
RF Frequency (MHz)
2000
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
Document No. 70-0162-03 │ UltraCMOS™ RFIC Solutions
4페이지 PE4308
Product Specification
Programming Options
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE4308. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.
Parallel Mode Interface
The parallel interface consists of five CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 5.
The parallel interface timing requirements are
defined by Figure 19 (Parallel Interface Timing
Diagram), Table 9 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 19) to latch new attenuation state into
device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
Table 5. Truth Table
P/S C16 C8 C4 C2 C1 Attenuation State
0 0 0 0 0 0 Reference Loss
0 0 000 1
1 dB
0 0 001 0
2 dB
0 0 010 0
4 dB
0 0 100 0
8 dB
0 1 000 0
16 dB
0 1 111 1
31 dB
Note: Not all 32 possible combinations of C1-C16 are shown.
Serial Interface
The PE4306’s serial interface is a 6-bit serial-in,
parallel-out shift register buffered by a transparent
latch. The latch is controlled by three CMOS-
compatible signals: Data, Clock, and Latch Enable
(LE). The Data and Clock inputs allow data to be
Document No. 70-0162-03 │ www.psemi.com
serially entered into the shift register, a process that
is independent of the state of the LE input.
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The stop bit (B0) of the data should
always be low to prevent an unknown state in the
device. The timing for this operation is defined by
Figure 18 (Serial Interface Timing Diagram) and
Table 8 (Serial Interface AC Characteristics).
Power-up Control Settings
The PE4308 always assumes a specifiable
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.
When the attenuator powers up in Serial mode (P/
S=1), the five control bits and a stop bit are set to
whatever data is present on the five parallel data
inputs (C1 to C16). This allows any one of the 32
attenuation settings to be specified as the power-up
state.
When the attenuator powers up in Parallel mode (P/
S=0) with LE=0, the control bits are automatically set
to one of four possible values. These four values
are selected by the two power-up control bits, PUP1
and PUP2, as shown in Table 6 (Power-Up Truth
Table, Parallel Mode).
Table 6. Power-Up Truth Table, Parallel
Interface Mode
P/S
0
0
0
0
0
Note:
LE PUP2 PUP1
00
0
00
1
01
0
01
1
1X X
Attenuation State
Reference Loss
8 dB
16 dB
31 dB
Defined by C1-C16
Power up with LE=1 provides normal parallel operation
with C1-C16, and PUP1 and PUP2 are not active.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
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부품번호 | 상세설명 및 기능 | 제조사 |
PE4302 | RF Digital Attenuator | Peregrine Semiconductor |
PE4304 | RF Digital Attenuator | Peregrine Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |