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PDF EM78P5830AA Data sheet ( Hoja de datos )
| Número de pieza | EM78P5830AA | |
| Descripción | 8-BIT MICRO-CONTROLLER | |
| Fabricantes | ELAN Microelectronics | |
| Logotipo |  |
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EM785830AA
8-BIT MICRO-CONTROLLER
Version 1.6
ELAN MICROELECTRONICS CORP.
No. 12, Innovation 1st RD., Science-Based Industrial Park
Hsin Chu City, Taiwan
TEL: (03) 5639977
FAX: (03)5630118
1 page  
IV. Pin Configuration
AVSS
P67
ADR/P66
AD6/P65
AD5/P64
AD4/P63
AD3/P62
XIN
XOUT
/RESET
P76/SCK
P75/SDO
P74/SDI
P73/INT3
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
PLLC
AVDD
NC
P97
P96
P95
P94
P93
P92
P91
P90
PC 2/PW M 2
PC 1/PW M 1
P70/INT0
EM785830AAP, EM785830AAM
EM78P5830AP, EM78P5830AM
EM78P5830AAP, EM78P5830AAM
Fig.1 Pin assignment
EM785830AA
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
12/1/2004 V1.6
5 Page 
EM785830AA
8-bit Micro-controller
R4 (RAM selection for common registers R20 ~ R3F))
(RAM selection register)
765 43210
RB1 RB0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0
R/W-0 R/W-0 R/W R/W R/W R/W R/W R/W
Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F
RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode.
Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F
These selection bits are used to determine which bank is activated among the 4 banks for 32 register (R20 to
R3F).
Please refer to VII.1 Operational registers for details.
R5 (PORT5 I/O data, Program page selection, SPI control , PWM control)
PAGE0 (PORT5 I/O data register, Program page register)
76543210
- - - - PS3 PS2 PS1 PS0
R/W-0 R/W-0 R/W-0 R/W-0
Bit 0 ~ Bit 3 (PS0 ~ PS3): Program page selection bits
PS3 PS2 PS1 PS0 Program memory page (Address)
0 0 0 0 Page 0
0 0 0 1 Page 1
0 0 1 0 Page 2
0 0 1 1 Page 3
: : : ::
: : : ::
1 1 1 0 Page 14
1 1 1 1 Page 15
User can use PAGE instruction to change page to maintain program page by user.
Bit 4: (undefined) not allowed to use. This bit must clear to 0 or some unpredicted wrong will occur.
Bit 5 ~ Bit 7: (undefined) not allowed to use. These bits are not sure be 0 or 1.
PAGE2 (SPI control)
76
RBF SPIE
R/W-0 R/W-0
5
SRO
R/W-0
4
SE
R/W-0
3
SCES
R/W-0
2
SBR2
R/W-0
1
SBR1
R/W-0
0
SBR0
R/W-0
Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits
SBR2
0
0
0
0
1
1
1
1
SBR1
0
0
1
1
0
0
1
1
SBR0
0
1
0
1
0
1
0
1
Mode
Master
Master
Master
Master
Master
Master
Slave
Master
Baud rate
Fsco
Fsco/2
Fsco/4
Fsco/8
Fsco/16
Fsco/32
16.384k
<Note> Fsco = CPU instruction clock
For example :
If PLL is enabled and main clock is selected to 3.5826MHz, the instruction clock is 3.5826MHz/2
Î Fsco=3.5862MHz/2
If PLL is enabled and main clock is selected to 3.5826MHz, the instruction clock is 0.895MHz/2
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
12/1/2004 V1.6
11 Page | ||
| Páginas | Total 30 Páginas | |
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