PDF AS4LC4M4F1 Data sheet ( Hoja de datos )

Número de pieza	AS4LC4M4F1
Descripción	4M x 4 CMOS DRAM
Fabricantes	Alliance Semiconductor
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No Preview Available ! www.DataSheet4U.com May 2001 AS4LC4M4F1 ® 4M×4 CMOS DRAM (Fast Page) 3.3V Family Features • Organization: 4,194,304 words × 4 bits • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time • Low power consumption - Active: 500 mW max - Standby: 3.6 mW max, CMOS I/O • Fast page mode • Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh • TTL-compatible, three-state I/O • JEDEC standard package - 300 mil, 24/26-pin SOJ • 3.3V power supply • Latch-up current ≥ 200 mA • ESD protection ≥ 2000 volts • Industrial and commercial temperature available Pin arrangement SOJ TSOP* VCC I/O0 I/O1 WE RAS NC 1 2 3 4 5 6 26 GND 25 I/O3 24 I/O2 23 CAS 22 OE 21 A9 VCC I/O0 I/O1 WE RAS NC 1 2 3 4 5 6 19 GND 18 I/O3 17 I/O2 16 CAS 15 OE 14 A9 A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13 19 A8 18 A7 17 A6 16 A5 15 A4 14 GND A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13 26 A8 25 A7 24 A6 23 A5 22 A4 21 GND *TSOP availability to be determined Pin designation Pin(s) Description A0 to A10 Address inputs RAS Row address strobe CAS Column address strobe WE Write enable I/O0 to I/O3 Input/output OE Output enable VCC GND Power Ground Selection guide Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum fast page mode cycle time Maximum operating current Maximum CMOS standby current Symbol tRAC tCAA tCAC tOEA tRC tPC ICC1 ICC5 AS4LC4M4F1-50 50 25 12 13 80 25 120 1.0 AS4LC4M4F1-60 60 30 15 15 100 30 110 1.0 Unit ns ns ns ns ns ns mA mA 5/16/01; v.1.0 Restored Alliance Semiconductor P. 1 of 14 Copyright © Alliance Semiconductor. All rights reserved. 1 page Write cycle Symbol tWCS tWCH tWP tRWL tCWL tDS tDH Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Read-modify-write cycle Symbol tRWC tRWD tCWD tAWD Parameter Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time Refresh cycle Symbol tCSR tCHR tRPC tCPT Parameter CAS setup time (CAS-before-RAS) CAS hold time (CAS-before-RAS) RAS precharge to CAS hold time CAS precharge time (CBR counter test) AS4LC4M4F1 ® -50 Min Max 0– 10 – 10 – 10 – 8– 0– 8– -60 Min Max 0– 10 – 10 – 10 – 10 – 0– 10 – Unit Notes ns 11 ns 11 ns ns ns ns 12 ns 12 -50 Min Max 113 – 67 – 32 – 42 – -60 Min Max 135 – 77 – 35 – 47 – Unit Notes ns ns 11 ns 11 ns 11 -50 Min Max 5– 8– 0– 10 -60 Min Max 5– 10 – 0– 10 – Unit Notes ns 3 ns 3 ns ns 5/16/01; v.1.0 Restored Alliance Semiconductor P. 5 of 14 5 Page Fast page mode early write waveform RAS tCRP CAS Address tASR tRAH tRCD tCSH tCAS tRAD Row tAR Column WE OE tHDR tDS tDH I/O Data In AS4LC4M4F1 ® tRASP tASC tWCS Column tPC tWCH tRWL tCAH tCP tRSH tRAL Column tCWL tWP tOEH Data in tOED Data in CAS before RAS refresh waveform RAS CAS tRP tRPC tCP tCSR DQ tRC tRAS tCHR OPEN WE = VIH RAS only refresh waveform RAS CAS Address tASR tCRP Row address tRAS tRAH WE = OE = VIH or VIL tRC tRP tRPC 5/16/01; v.1.0 Restored Alliance Semiconductor P. 11 of 14 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AS4LC4M4F1	4M x 4 CMOS DRAM	Alliance Semiconductor

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